NAND memory cell string having a stacked select gate structure and process for for forming same
A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source a...
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Main Authors | , , , |
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Format | Patent |
Language | English |
Published |
31.07.2018
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Subjects | |
Online Access | Get full text |
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