Memory device

A memory device includes a first rank having first memory banks and a first quad skew adjustment circuit and a second rank having second memory banks and a second quad skew adjustment circuit, wherein each of the first quad skew adjustment circuit and the second quad skew adjustment circuit is confi...

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Bibliographic Details
Main Authors SUNG, YOOCHANG, YOO, CHANGSIK, KIM, YONGHUN, CHOI, JAEMIN, JEONG, JAEWOO
Format Patent
LanguageChinese
English
Published 11.10.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory device includes a first rank having first memory banks and a first quad skew adjustment circuit and a second rank having second memory banks and a second quad skew adjustment circuit, wherein each of the first quad skew adjustment circuit and the second quad skew adjustment circuit is configured to: receive a 4-phase clock through first channels; detect internal quad skew of the 4-phase clock; correct skew of the 4-phase clock according to the detected quad skew; and output mode register information corresponding to the detected quad skew through a second channel.
Bibliography:Application Number: TW202211128170