Processor,computer system,computer program product and method to manage instruction cache prefetching from an instruction cache

Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common...

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Main Authors LUPON, MARC, KOTSELIDIS, CHRISTOS E, GIBERT CODINA, ENRIC, LATORRE, FERNANDO, MAGKLIS, GRIGORIOS, PAVLOU, DEMOS, MARTINEZ VICENTE, ALEJANDRO, LOPEZ, PEDRO, MARCUELLO, PEDRO, GONZALEZ, ANTONIO, XEKALAKIS, POLYCHRONIS, MARTINEZ, RAUL, HYUSEINOVA, MIREM, ORTEGA, DANIEL, CODINA, JOSEP M, GOMEZ REQUENA, CRISPIN, TOURNAVITIS, GEORGIOS, MADRILES, CARLOS, STAVROU, KYRIAKOS A
Format Patent
LanguageChinese
English
Published 01.04.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Abstract Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
AbstractList Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
Author GOMEZ REQUENA, CRISPIN
LOPEZ, PEDRO
MARTINEZ VICENTE, ALEJANDRO
GONZALEZ, ANTONIO
MARCUELLO, PEDRO
TOURNAVITIS, GEORGIOS
MADRILES, CARLOS
HYUSEINOVA, MIREM
CODINA, JOSEP M
KOTSELIDIS, CHRISTOS E
GIBERT CODINA, ENRIC
ORTEGA, DANIEL
LATORRE, FERNANDO
PAVLOU, DEMOS
STAVROU, KYRIAKOS A
LUPON, MARC
XEKALAKIS, POLYCHRONIS
MAGKLIS, GRIGORIOS
MARTINEZ, RAUL
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– fullname: ORTEGA, DANIEL
– fullname: CODINA, JOSEP M
– fullname: GOMEZ REQUENA, CRISPIN
– fullname: TOURNAVITIS, GEORGIOS
– fullname: MADRILES, CARLOS
– fullname: STAVROU, KYRIAKOS A
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Snippet Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch...
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SubjectTerms CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Title Processor,computer system,computer program product and method to manage instruction cache prefetching from an instruction cache
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