Low power set associative cache
A processor having an L1 cache memory that may use a compare circuit to determine matches of stored tag information against an address and gate sense amps of the cache memory with a cache-hit signal.
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English |
Published |
11.11.2005
|
Edition | 7 |
Subjects | |
Online Access | Get full text |
Cover
Loading…
Be the first to leave a comment!