Low power set associative cache

• Main Authors: MILLER, JAY B, CLARK, LAWRENCE T
• Format: Patent
• Language: English
• Published: 11.11.2005
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A processor having an L1 cache memory that may use a compare circuit to determine matches of stored tag information against an address and gate sense amps of the cache memory with a cache-hit signal.