Memory system and the methods for operating the same

A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrica...

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Main Authors LUNG, HSIANG-LAN, CHIEN, WEIIH, MILLER, CHRISTOPHER P, GONG, NAN-BO, BRIGHTSKY, MATTHEW JOSEPH
Format Patent
LanguageChinese
English
Published 01.08.2021
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Abstract A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.
AbstractList A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.
Author BRIGHTSKY, MATTHEW JOSEPH
MILLER, CHRISTOPHER P
GONG, NAN-BO
LUNG, HSIANG-LAN
CHIEN, WEIIH
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Snippet A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a...
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SubjectTerms INFORMATION STORAGE
PHYSICS
STATIC STORES
Title Memory system and the methods for operating the same
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