Layout method and semiconductor device
A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and...
Saved in:
Main Authors | , , , , |
---|---|
Format | Patent |
Language | Chinese English |
Published |
16.01.2018
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines. |
---|---|
AbstractList | A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines. |
Author | YANG, JAE-SEOK OH, IN-WOOK HWANG, SUNG-WOOK LEE, JONG-HYUN LEE, HYUN-JAE |
Author_xml | – fullname: HWANG, SUNG-WOOK – fullname: LEE, JONG-HYUN – fullname: YANG, JAE-SEOK – fullname: LEE, HYUN-JAE – fullname: OH, IN-WOOK |
BookMark | eNrjYmDJy89L5WRQ80mszC8tUchNLcnIT1FIzEtRKE7NzUzOz0spTS7JL1JISS3LTE7lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxIeFGBoYWBsaGhqaOxsSoAQBnBimK |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
ExternalDocumentID | TW201803115A |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_TW201803115A3 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 15:20:10 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | Chinese English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_TW201803115A3 |
Notes | Application Number: TW20176110933 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180116&DB=EPODOC&CC=TW&NR=201803115A |
ParticipantIDs | epo_espacenet_TW201803115A |
PublicationCentury | 2000 |
PublicationDate | 20180116 |
PublicationDateYYYYMMDD | 2018-01-16 |
PublicationDate_xml | – month: 01 year: 2018 text: 20180116 day: 16 |
PublicationDecade | 2010 |
PublicationYear | 2018 |
RelatedCompanies | SAMSUNG ELECTRONICS CO., LTD |
RelatedCompanies_xml | – name: SAMSUNG ELECTRONICS CO., LTD |
Score | 3.2476618 |
Snippet | A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | Layout method and semiconductor device |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180116&DB=EPODOC&locale=&CC=TW&NR=201803115A |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQSTJMtExOMjfTTU1JTNI1MTVM0k00STTQtUwD1o5p5happimgvcO-fmYeoSZeEaYRTAxZsL0w4HNCy8GHIwJzVDIwv5eAy-sCxCCWC3htZbF-UiZQKN_eLcTWRQ3aOza0AM0rqLk42boG-Lv4O6s5O9uGhKv5BUHkQCfLODIzsIKa0aBz9l3DnEC7UgqQqxQ3QQa2AKBpeSVCDExVGcIMnM6wm9eEGTh8oRPeQCY07xWLMKj5JFbml5YoQO58VkjMS1EoBq1sz88DHdmaX6SQkgrK9aIMim6uIc4eukAL4-G-iw8JR7jNWIyBBdjrT5VgUDA3NE0EZhhjE2OzVBOLZMNE81TzVBMzs0Tj5DTz5GQDSQYp3OZI4ZOUZuACcUDjCIZmMgwsJUWlqbLAmrUkSQ4cJAA9R31F |
link.rule.ids | 230,309,786,891,25594,76903 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQSTJMtExOMjfTTU1JTNI1MTVM0k00STTQtUwD1o5p5happimgvcO-fmYeoSZeEaYRTAxZsL0w4HNCy8GHIwJzVDIwv5eAy-sCxCCWC3htZbF-UiZQKN_eLcTWRQ3aOza0AM0rqLk42boG-Lv4O6s5O9uGhKv5BUHkQCfLODIzsJoDu4TgrlKYE2hXSgFyleImyMAWADQtr0SIgakqQ5iB0xl285owA4cvdMIbyITmvWIRBjWfxMr80hIFyJ3PCol5KQrFoJXt-XmgI1vzixRSUkG5XpRB0c01xNlDF2hhPNx38SHhCLcZizGwAHv9qRIMCuaGponADGNsYmyWamKRbJhonmqeamJmlmicnGaenGwgySCF2xwpfJLyDJweIb4-8T6eft7SDFwgCdCYgqGZDANLSVFpqiywli1JkgMHDwA9lYAv |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Layout+method+and+semiconductor+device&rft.inventor=HWANG%2C+SUNG-WOOK&rft.inventor=LEE%2C+JONG-HYUN&rft.inventor=YANG%2C+JAE-SEOK&rft.inventor=LEE%2C+HYUN-JAE&rft.inventor=OH%2C+IN-WOOK&rft.date=2018-01-16&rft.externalDBID=A&rft.externalDocID=TW201803115A |