Integrated circuit and method of semiconductor device fabrication

• Main Authors: SUN, CHIH-TING, LI, ZI-KUAN, CHANG, MENG-LIN, LO, TSENGIN, TSEN, YA-WEN, LIN, GENG-HE, CHANG, BO-SEN
• Format: Patent
• Language: Chinese; English
• Published: 16.01.2018
• Subjects: BASIC ELECTRIC ELEMENTS; CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; PHYSICS; SEMICONDUCTOR DEVICES

Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.