NAND memory unit, NAND memory array, and methods for operating them

A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least o...

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Main Authors LIN, WEI, MITIUKHINA, NINA, SHIROTA, RIICHIRO, KUO, TSAI-HAO
Format Patent
LanguageChinese
English
Published 01.12.2013
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Abstract A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.
AbstractList A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.
Author LIN, WEI
MITIUKHINA, NINA
KUO, TSAI-HAO
SHIROTA, RIICHIRO
Author_xml – fullname: LIN, WEI
– fullname: MITIUKHINA, NINA
– fullname: SHIROTA, RIICHIRO
– fullname: KUO, TSAI-HAO
BookMark eNrjYmDJy89L5WRw9nP0c1HITc3NL6pUKM3LLNFRQBZJLCpKrNRRSMxLAYqUZOSnFCuk5Rcp5BekFiWWZOalK5RkpObyMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjU4oLE5NS81JL4kHAjA0NjE0tjSxNHY2LUAADOjDLy
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID TW201349394A
GroupedDBID EVB
ID FETCH-epo_espacenet_TW201349394A3
IEDL.DBID EVB
IngestDate Fri Jul 19 12:28:37 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language Chinese
English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_TW201349394A3
Notes Application Number: TW20120117996
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131201&DB=EPODOC&CC=TW&NR=201349394A
ParticipantIDs epo_espacenet_TW201349394A
PublicationCentury 2000
PublicationDate 20131201
PublicationDateYYYYMMDD 2013-12-01
PublicationDate_xml – month: 12
  year: 2013
  text: 20131201
  day: 01
PublicationDecade 2010
PublicationYear 2013
RelatedCompanies PHISON ELECTRONICS CORP
RelatedCompanies_xml – name: PHISON ELECTRONICS CORP
Score 3.0267365
Snippet A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title NAND memory unit, NAND memory array, and methods for operating them
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131201&DB=EPODOC&locale=&CC=TW&NR=201349394A
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_mFPVNp6LzgwjSpxVbm7Xrw5Ct7RjCuiHV7W2kaYYKdmXrkPnXe8k6txd9CckdHEngl7sk9wFwZ3IukrghdJu7jk65YHqDuqbO644hjISyRDlj9kK7-0KfRvVRCT7WsTAqT-iXSo6IiOKI91yd19nmEctXvpXz-_gdSdPHTtT0teJ2bFomNprfbgaDvt_3NM9rRkMtfFY86loube3ALprRjkRD8NqWUSnZtkrpHMHeAKWl-TGUvt8qcOCtK69VYL9XfHhjt8De_AS8sBX65FN6xi7JApFYI9sUNpuxZY2wNCGrqtBzgvYomWYyazLqJyLTs57CbSeIvK6Osxn_Ln0cDTcTt86gnE5TcQ4E71iWsA06cWxBJzJMjomEU04NlrBYPFxA9W851f-Yl3AoByuHjSso57OFuEa1m8c3ar9-ANJZhyQ
link.rule.ids 230,309,783,888,25576,76876
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dT8IwEL8gGvFNUaP4VROzJxY3Vzb2QAxsEFQYxEzhjXRdiZo4CIwY_Ou9FhBe9KVpesnl2uTXu2vvA-DG5FzEUVnoNncdnXLB9DJ1TZ2XHEMYMWWxCsZsB3bzhT72S_0MfKxyYVSd0C9VHBERxRHvqbqvx-tHLF_FVk5vo3dcGt03woqvLb1j0zJx0Pxapd7t-B1P87xK2NOCZ0WjruXS6hZso4ntSDTUX2syK2W8qVIa-7DTRW5JegCZ77c85LxV57U87LaXH944XWJvegheUA188ikjY-dkhkgsks0VNpmweZGwJCaLrtBTgvYoGY1l1WTUT0SWZz2C60Y99Jo6SjP43fog7K0Ft44hm4wScQIEfSxL2AYdOragQ5kmx0TMKacGi1kk7k6h8Defwn_EK8g1w3Zr0HoIns5gTxIWwRvnkE0nM3GBKjiNLtXZ_QBU-IoX
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=NAND+memory+unit%2C+NAND+memory+array%2C+and+methods+for+operating+them&rft.inventor=LIN%2C+WEI&rft.inventor=MITIUKHINA%2C+NINA&rft.inventor=SHIROTA%2C+RIICHIRO&rft.inventor=KUO%2C+TSAI-HAO&rft.date=2013-12-01&rft.externalDBID=A&rft.externalDocID=TW201349394A