Wafer level chip packaging

• Main Authors: HECHT, ILYA, HUMPSTON, GILES, OGANESIAN, VAGE, AKSENTON, YULIA, DAYAN, AVI, NYSTROM, MICHAEL J, GRINMAN, ANDREY, REIFEL, MITCHELL HAYES, BURTZLAFF, ROBERT, ROSENSTEIN, CHARLES, HAZANOVICH, FELIX, OVRUTSKY, DAVID, AVSIAN, OSHER
• Format: Patent
• Language: Chinese; English
• Published: 16.10.2007
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.