Method of creating high-quality relaxed SiGe-on-insulator for strained Si cmos applications

• Main Authors: FOGEL, KEITH E, OTT, JOHN A, DEVENDRA K. SADANA, BEDELL, STEPHEN W, CHU, JACK O, KOESTER, STEVEN J
• Format: Patent
• Language: Chinese; English
• Published: 01.12.2003
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to the diffusion of Ge. Optionally forming a Si cap layer over the SiGe or pure Ge layer, and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughout the first single crystal Si layer, the optional Si cap and the SiGe or pure Ge layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate materials are also disclosed herein.