DIE ENCAPSULATION IN OXIDE BONDED WAFER STACK

jjrzygraiii 11411111111111111111 , 411 11 112 112 FIG. 2A 210 \" - - I W4 1W e ji l i r l- , ' WM 224N, 208 .. 208 M r . . .. E N . IP RIM 206 11.11111 - 111101111 ii - 1.* 212 214 216 218 202 204 200 ,, . ./2c0 W O 20 18/ 2127 85 Al PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) Iiii...

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Main Authors DRAB, John J, MILNE, Jason G
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LanguageEnglish
Published 27.09.2019
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Abstract jjrzygraiii 11411111111111111111 , 411 11 112 112 FIG. 2A 210 \" - - I W4 1W e ji l i r l- , ' WM 224N, 208 .. 208 M r . . .. E N . IP RIM 206 11.11111 - 111101111 ii - 1.* 212 214 216 218 202 204 200 ,, . ./2c0 W O 20 18/ 2127 85 Al PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) Iiiimmolimmuminiolomolownionommill (10) International Publication Number WO 2018/212785 Al WIPO I PCT (12) INTERNATIONAL APPLICATION (19) World Intellectual Property Organization International Bureau (43) International Publication Date 22 November 2018 (22.11.2018) FIG. 3D (51) International Patent Classification: H01L 25/065 (2006.01) HOlL 21/50 (2006.01) H01L 21/98 (2006.01) H01L 21/54 (2006.01) H01L 23/10 (2006.01) (21) International Application Number: PCT/US2017/061922 (22) International Filing Date: 16 November 2017 (16.11.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/596,663 16 May 2017 (16.05.2017) US (71) Applicant: RAYTHEON COMPANY [US/US]; 870 Winter Street, Waltham, Massachusetts 02451-1449 (US). (72) Inventors: DRAB, John J.; c/o Raytheon Company, 870 Winter Street, Waltham, Massachusetts 02451-1449 (US). MILNE, Jason G.; c/o Raytheon Company, 870 Winter Street, Waltham, Massachusetts 02451-1449 (US). (74) Agent: MARAIA, Joseph M. et al.; Burns & Levinson LLP, 125 Summer Street, Boston, Massachusetts 02110 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, (54) Title: DIE ENCAPSULATION IN OXIDE BONDED WAFER STACK (57) : Structures and methods of fabricating semicon- ductor wafer assemblies (100) that encapsulate at least one die (108, 202, 402) in a cavity (110, 204, 404) etched into an oxide bonded semiconductor wafer stack (102+104, 206+208, 406+408). The methods generally include the steps of position- ing the die (108, 202, 402) in the cavity (110, 204, 404), me- chanically and electrically mounting the die (108, 202, 402) to the wafer stack (102+104, 206+208, 406+408), and encapsulat- ing the die (108, 202, 402) within the cavity (110, 204, 404) by bonding a lid wafer (106, 210, 410) to the wafer stack (102+104, 206+208, 406+408) in one of multiple ways. Semiconductor pro- cessing steps are applied to construct the assemblies (e.g., deposi- tion, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embod- 224 iments described above. The cavity (110, 404) may be hermeti- cally sealed to encapsulate the semiconductor die (108, 402). The wafer assembly (100) may be diced to produce one or more semi- conductor chips, each semiconductor chip including one or more encapsulated semiconductor die (108, 202, 402). A thermal inter- face (164, 170, 412) may be comprised between the semiconduc- tor die (108, 402) and one or more of the wafers (102, 104, 106, 406, 408, 410). The wafer stack (102+104, 406+408) and the lid 222 wafer (106, 410) may be oxide bonded together. Alternatively, the wafer stack (206+208) and the lid wafer (210) may be bump (214) bonded so as to define an air gap (224) providing thermal isolation from the cavity (204). One of the wafers (102, 104, 106) may define a conduit (168) to the cavity (110) from the exterior of the wafer assembly (100), [Continued on next page] WO 2018/212785 Al MIDEDIMOMMIDIREIDIHIHOHOMMODEVON SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: - with international search report (Art. 21(3)) wherein the conduit (168) and the cavity (110) are at least partially filled with a thermally conductive material, are evacuated and sealed providing a vacuum package or are evacuated and backfilled with a liquid or gas before sealing.
AbstractList jjrzygraiii 11411111111111111111 , 411 11 112 112 FIG. 2A 210 \" - - I W4 1W e ji l i r l- , ' WM 224N, 208 .. 208 M r . . .. E N . IP RIM 206 11.11111 - 111101111 ii - 1.* 212 214 216 218 202 204 200 ,, . ./2c0 W O 20 18/ 2127 85 Al PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) Iiiimmolimmuminiolomolownionommill (10) International Publication Number WO 2018/212785 Al WIPO I PCT (12) INTERNATIONAL APPLICATION (19) World Intellectual Property Organization International Bureau (43) International Publication Date 22 November 2018 (22.11.2018) FIG. 3D (51) International Patent Classification: H01L 25/065 (2006.01) HOlL 21/50 (2006.01) H01L 21/98 (2006.01) H01L 21/54 (2006.01) H01L 23/10 (2006.01) (21) International Application Number: PCT/US2017/061922 (22) International Filing Date: 16 November 2017 (16.11.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/596,663 16 May 2017 (16.05.2017) US (71) Applicant: RAYTHEON COMPANY [US/US]; 870 Winter Street, Waltham, Massachusetts 02451-1449 (US). (72) Inventors: DRAB, John J.; c/o Raytheon Company, 870 Winter Street, Waltham, Massachusetts 02451-1449 (US). MILNE, Jason G.; c/o Raytheon Company, 870 Winter Street, Waltham, Massachusetts 02451-1449 (US). (74) Agent: MARAIA, Joseph M. et al.; Burns & Levinson LLP, 125 Summer Street, Boston, Massachusetts 02110 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, (54) Title: DIE ENCAPSULATION IN OXIDE BONDED WAFER STACK (57) : Structures and methods of fabricating semicon- ductor wafer assemblies (100) that encapsulate at least one die (108, 202, 402) in a cavity (110, 204, 404) etched into an oxide bonded semiconductor wafer stack (102+104, 206+208, 406+408). The methods generally include the steps of position- ing the die (108, 202, 402) in the cavity (110, 204, 404), me- chanically and electrically mounting the die (108, 202, 402) to the wafer stack (102+104, 206+208, 406+408), and encapsulat- ing the die (108, 202, 402) within the cavity (110, 204, 404) by bonding a lid wafer (106, 210, 410) to the wafer stack (102+104, 206+208, 406+408) in one of multiple ways. Semiconductor pro- cessing steps are applied to construct the assemblies (e.g., deposi- tion, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embod- 224 iments described above. The cavity (110, 404) may be hermeti- cally sealed to encapsulate the semiconductor die (108, 402). The wafer assembly (100) may be diced to produce one or more semi- conductor chips, each semiconductor chip including one or more encapsulated semiconductor die (108, 202, 402). A thermal inter- face (164, 170, 412) may be comprised between the semiconduc- tor die (108, 402) and one or more of the wafers (102, 104, 106, 406, 408, 410). The wafer stack (102+104, 406+408) and the lid 222 wafer (106, 410) may be oxide bonded together. Alternatively, the wafer stack (206+208) and the lid wafer (210) may be bump (214) bonded so as to define an air gap (224) providing thermal isolation from the cavity (204). One of the wafers (102, 104, 106) may define a conduit (168) to the cavity (110) from the exterior of the wafer assembly (100), [Continued on next page] WO 2018/212785 Al MIDEDIMOMMIDIREIDIHIHOHOMMODEVON SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: - with international search report (Art. 21(3)) wherein the conduit (168) and the cavity (110) are at least partially filled with a thermally conductive material, are evacuated and sealed providing a vacuum package or are evacuated and backfilled with a liquid or gas before sealing.
Author DRAB, John J
MILNE, Jason G
Author_xml – fullname: DRAB, John J
– fullname: MILNE, Jason G
BookMark eNrjYmDJy89L5WTQdfF0VXD1c3YMCA71cQzx9PdT8PRT8I_wdHFVcPL3c3F1UQh3dHMNUggOcXT25mFgTUvMKU7lhdLcDCpuriHOHrqpBfnxqcUFicmpeakl8cHuhoZGBoaWBuaGxsYRjsZEKgMAeQooYQ
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID SG11201907133XA
GroupedDBID EVB
ID FETCH-epo_espacenet_SG11201907133XA3
IEDL.DBID EVB
IngestDate Fri Jul 19 14:40:36 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_SG11201907133XA3
Notes Application Number: SG20191107133X
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190927&DB=EPODOC&CC=SG&NR=11201907133XA
ParticipantIDs epo_espacenet_SG11201907133XA
PublicationCentury 2000
PublicationDate 20190927
PublicationDateYYYYMMDD 2019-09-27
PublicationDate_xml – month: 09
  year: 2019
  text: 20190927
  day: 27
PublicationDecade 2010
PublicationYear 2019
RelatedCompanies RAYTHEON COMPANY
RelatedCompanies_xml – name: RAYTHEON COMPANY
Score 3.2225125
Snippet jjrzygraiii 11411111111111111111 , 411 11 112 112 FIG. 2A 210 \" - - I W4 1W e ji l i r l- , ' WM 224N, 208 .. 208 M r . . .. E N . IP RIM 206 11.11111 -...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title DIE ENCAPSULATION IN OXIDE BONDED WAFER STACK
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190927&DB=EPODOC&locale=&CC=SG&NR=11201907133XA
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwhV1LT8JAEJ4gGvWmqPGF2QPprZFHW8qhMWV3C6i0hIL2Rui2TTxYiNT4953dFB8Xve0jmX0k3843szO7AI2klyUCaSriW1i6_OVIt5dZootWFpvLJhIOlfU-9q3h3LiPzKgCr9tcGPVO6Id6HBERJRDvhTqv199OLKZiKze38Qs2re68mcO00jpG7dZrdzXWd_gkYAHVKHXCgeZPHaQVsleaZJG7A7vIpLsSEPypLxNT1j-1incEexMUmBfHUEnzGhzQ7edrNdgfl3feWCzhtzkBHckb4T51J-H8UTmXyMgnQTRinPQDn3FGnl2PT0k4c-nDKTQ8PqNDHcddfK1zEQ5-zbJzBtV8lafnQLK4GQuk9mbS6RhWy7LtxLRFK7VMtLZiQ1xA_U9Rl__0X8GhrMk4iHb3GqrF23taR2VbxDdqiz4B0md8sQ
link.rule.ids 230,309,783,888,25576,76876
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwhV1LT8JAEJ4gGvGmqPGF7oH01giUlnJoTNltAYGW0KK9EbptEw8WIjX-fWc34OOit81OMvtIvp1vZndmAepJN0s40lTENzdU8cuRai6zROXNLNaXDSQcMut94hmDefsx0qMSvO5yYWSd0A9ZHBERxRHvhTyv199BLCbfVm7u4xfsWj24ocWUrXeM1q3b6iisZzlTn_lUodQK-oo3s5BWCKlwySJ7D_aRZXcEIJynnkhMWf-0Ku4xHExRYV6cQCnNq1Chu8_XqnA42d55Y3MLv80pqEjeiONRexrMxzK4RIYe8aMhc0jP95jDyLPtOjMShDYdnUHddUI6UHHcxdc6F0H_1yy1cyjnqzy9AJLFjZgjtdcTTWsbTcM0E93kzdTQ0duK2_wSan-quvpHfgeVQTgZL8ZDb3QNR0Ii3kS0OjdQLt7e0xoa3iK-ldv1CdYuf6Q
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=DIE+ENCAPSULATION+IN+OXIDE+BONDED+WAFER+STACK&rft.inventor=DRAB%2C+John+J&rft.inventor=MILNE%2C+Jason+G&rft.date=2019-09-27&rft.externalDBID=A&rft.externalDocID=SG11201907133XA