CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, A memory device is provided, comprising:a substrate;a lower conductive line (22) disposed above the substrate and extending in...

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Main Authors TORTORELLI, INNOCENZO, RAVASIO, MARCELLO, SCIARRILLO, SAMUELE, MOTTADELLI, RICCARDO, SOMASCHINI, ROBERTO, PELLIZZER, FABIO, CASELLATO, CRISTINA
Format Patent
LanguageEnglish
Published 29.09.2016
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Abstract The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, A memory device is provided, comprising:a substrate;a lower conductive line (22) disposed above the substrate and extending in a first direction and an upper conductive line (20) disposed above the lower conductive line (22) and extending in the second direction crossing the first direction; anda memory cell stack (30) between the lower (22) and upper (20) conductive lines, the memory cell stack (30) comprising:a storage element (34);and a lateral plateau region between the storage element (34) and the lower conductive line (22) such that the width of the memory cell stack immediately below the plateau region to the lower conductive line (22) is greater compared the width of the cell stack immediately above the plateau region to the upper conductive line (20).
AbstractList The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, A memory device is provided, comprising:a substrate;a lower conductive line (22) disposed above the substrate and extending in a first direction and an upper conductive line (20) disposed above the lower conductive line (22) and extending in the second direction crossing the first direction; anda memory cell stack (30) between the lower (22) and upper (20) conductive lines, the memory cell stack (30) comprising:a storage element (34);and a lateral plateau region between the storage element (34) and the lower conductive line (22) such that the width of the memory cell stack immediately below the plateau region to the lower conductive line (22) is greater compared the width of the cell stack immediately above the plateau region to the upper conductive line (20).
Author TORTORELLI, INNOCENZO
SOMASCHINI, ROBERTO
MOTTADELLI, RICCARDO
SCIARRILLO, SAMUELE
PELLIZZER, FABIO
CASELLATO, CRISTINA
RAVASIO, MARCELLO
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– fullname: MOTTADELLI, RICCARDO
– fullname: SOMASCHINI, ROBERTO
– fullname: PELLIZZER, FABIO
– fullname: CASELLATO, CRISTINA
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Snippet The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same....
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SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
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