METHOD OF FABRICATING A STACKED POLY-POLY AND MOS CAPACITOR USING A SIGE INTEGRATION SCHEME

• Main Authors: JAMES STUART DUNN, DOUGLAS DUANE COOLBAUGH, STEPHEN ARTHUR ST. ONGE
• Format: Patent
• Language: English
• Published: 29.12.2004
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.