RECEIVING INTERRUPT BLOCKING CIRCUIT IN BCH CODEC

The reception interrupt blocking circuit in a BCH codec comprises a synchronization pattern sensing unit for sensing the synchronization pattern for a receiving data; a power off sensing unit for sensing the power off state for the receiving data; a first latch circuit stopping generation of a first...

Full description

Saved in:
Bibliographic Details
Main Author KIM, KYU - HAK
Format Patent
LanguageEnglish
Korean
Published 16.11.1995
Edition6
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Online AccessGet full text

Cover

Be the first to leave a comment!
You must be logged in first