RECEIVING INTERRUPT BLOCKING CIRCUIT IN BCH CODEC

The reception interrupt blocking circuit in a BCH codec comprises a synchronization pattern sensing unit for sensing the synchronization pattern for a receiving data; a power off sensing unit for sensing the power off state for the receiving data; a first latch circuit stopping generation of a first...

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Bibliographic Details
Main Author KIM, KYU - HAK
Format Patent
LanguageEnglish
Korean
Published 16.11.1995
Edition6
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:The reception interrupt blocking circuit in a BCH codec comprises a synchronization pattern sensing unit for sensing the synchronization pattern for a receiving data; a power off sensing unit for sensing the power off state for the receiving data; a first latch circuit stopping generation of a first interrupt condition signal by the output of the power off sensing unit and generating the first interrupt condition signal if there is an output of the synchronization pattern sensing unit; a FIFO for sequentially inputting and outputting the receiving data; a synchronization pattern correlating unit for correlating the synchronization pattern of the output synchronization pattern data of the FIFO; an interrupt condition generating unit for generating the output "S" data to the second latch circuit as a second interrupt condition signal according to the output of the synchronization pattern correlating unit; and a receiving interrupt signal generating unit for generating a receiving interrupt signal by the first and second interrupt condition signals.
Bibliography:Application Number: KR19920021134