SEMICONDUCTOR MEMORY DEVICE

A main row decoder for driving main word lines in a main memory cell array includes partial decoders the number of which is equal to the number of the main word lines. Each partial decoder includes a NAND gate for receiving row address signals, an inverter for driving a corresponding main word line...

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Bibliographic Details
Main Authors MATSUI, MASATAKA 3, ISOBE, MITSUO, HAMANO, TAKAHIRO
Format Patent
LanguageEnglish
Korean
Published 08.07.1994
Edition5
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A main row decoder for driving main word lines in a main memory cell array includes partial decoders the number of which is equal to the number of the main word lines. Each partial decoder includes a NAND gate for receiving row address signals, an inverter for driving a corresponding main word line in response to an output from the NAND gate, a fuse element connected between the output terminal of the NAND gate and the input terminal of the inverter, and a MOS transistor connected between the input terminal of the inverter and a power supply voltage.
Bibliography:Application Number: KR19890004078