INTERRUPT CONTROLLER

In an interrupt control unit (1), an interrupt mask circuit (2) has at least one interrupt mask bit. This interrupt mask bit decides whether the unit is set to an interrupt enabled state or interrupt disabled state. In this invention, said mask bit is connected to a received channel inform line (32)...

Full description

Saved in:
Bibliographic Details
Main Author TERUYAMA, TATSUO
Format Patent
LanguageEnglish
Korean
Published 23.06.1994
Edition5
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:In an interrupt control unit (1), an interrupt mask circuit (2) has at least one interrupt mask bit. This interrupt mask bit decides whether the unit is set to an interrupt enabled state or interrupt disabled state. In this invention, said mask bit is connected to a received channel inform line (32) from which said mask bit is informed of the acceptance of interruptions by an outside processor (40). Having been informed of said acceptance through said received channel inform line (32), said mask bit is set to an interrupt disabled state so as to prohibit the execution of successive interruptions. As a result, the interrupt overflow, especially in the level 0, can be effectively prevented.
Bibliography:Application Number: KR19910012989