SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE COMPRISING THE SAME

• Main Authors: LEE YUN TAE, LEE JIN WON
• Format: Patent
• Language: English; Korean
• Published: 07.07.2023
• Subjects: BASIC ELECTRIC ELEMENTS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS; PRINTED CIRCUITS; SEMICONDUCTOR DEVICES

The present disclosure relates to a semiconductor package. The semiconductor package includes: a semiconductor chip including a FEOL (Front End Of Line) layer and a first BEOL (Back End Of Line) layer disposed on the FEOL layer; and a printed circuit board including a wiring layer and a second BEOL layer disposed on the wiring layer. The semiconductor chip is mounted on the printed circuit board to make the first and second BEOL layers face each other and them connect with each other. The second BEOL layer includes wiring for power transmission. Therefore, it is possible to reduce process costs. 본 개시는 페올(FEOL: Front End Of Line)층, 및 상기 페올층 상에 배치되는 제1베올(BEOL: Back End Of Line)층을 포함하는 반도체칩; 및 배선층, 및 상기 배선층 상에 배치되는 제2베올층을 포함하는 인쇄회로기판; 을 포함하며, 상기 반도체칩은 상기 제1 및 제2베올층이 서로 마주보며 서로 연결되도록 상기 인쇄회로기판 상에 실장되며, 상기 제2베올층은 파워 전송용 배선을 포함하는, 반도체 패키지에 관한 것이다.