Memory device and method for controlling row hammer
Disclosed are a row hammer control method to prevent a row hammer address from being expelled from a register, and a memory device. According to the present invention, the memory device comprises: a memory cell array including a word line and a plurality of counter memory cells storing access the co...
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Format | Patent |
Language | English Korean |
Published |
15.06.2023
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Abstract | Disclosed are a row hammer control method to prevent a row hammer address from being expelled from a register, and a memory device. According to the present invention, the memory device comprises: a memory cell array including a word line and a plurality of counter memory cells storing access the count value of the word line; and a control logic circuit monitoring a row address accessing the word line during a row hammer monitoring time frame, determining the row address as a row hammer address when the number of accesses to the word line is greater than a threshold and storing the row address in an address storage unit. The control logic circuit holds a determination operation for the next row hammer address on the basis of activation of a latch pull signal indicating that there is no free space to store the row hammer address in the address storage unit.
로우 해머 제어 방법 및 메모리 장치가 개시된다. 메모리 장치는 워드라인과 워드라인의 억세스 카운트 값을 저장하는 복수의 카운터 메모리 셀들을 포함하는 메모리 셀 어레이 및 로우 해머 모니터링 시간 프레임 동안 워드라인을 억세스하는 로우 어드레스를 모니터링하고 워드라인에 대한 억세스 회수가 임계치 이상일 때 로우 어드레스를 로우 해머 어드레스로 판단하여 어드레스 저장부에 저장하는 제어 로직 회로를 포함한다. 제어 로직 회로는 어드레스 저장부에 로우 해머 어드레스를 저장할 빈 공간이 없음을 나타내는 래치 풀 신호의 활성화에 기초하여 다음 로우 해머 어드레스에 대한 판단 동작을 홀드한다. |
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AbstractList | Disclosed are a row hammer control method to prevent a row hammer address from being expelled from a register, and a memory device. According to the present invention, the memory device comprises: a memory cell array including a word line and a plurality of counter memory cells storing access the count value of the word line; and a control logic circuit monitoring a row address accessing the word line during a row hammer monitoring time frame, determining the row address as a row hammer address when the number of accesses to the word line is greater than a threshold and storing the row address in an address storage unit. The control logic circuit holds a determination operation for the next row hammer address on the basis of activation of a latch pull signal indicating that there is no free space to store the row hammer address in the address storage unit.
로우 해머 제어 방법 및 메모리 장치가 개시된다. 메모리 장치는 워드라인과 워드라인의 억세스 카운트 값을 저장하는 복수의 카운터 메모리 셀들을 포함하는 메모리 셀 어레이 및 로우 해머 모니터링 시간 프레임 동안 워드라인을 억세스하는 로우 어드레스를 모니터링하고 워드라인에 대한 억세스 회수가 임계치 이상일 때 로우 어드레스를 로우 해머 어드레스로 판단하여 어드레스 저장부에 저장하는 제어 로직 회로를 포함한다. 제어 로직 회로는 어드레스 저장부에 로우 해머 어드레스를 저장할 빈 공간이 없음을 나타내는 래치 풀 신호의 활성화에 기초하여 다음 로우 해머 어드레스에 대한 판단 동작을 홀드한다. |
Author | CHO SEONG JIN |
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Snippet | Disclosed are a row hammer control method to prevent a row hammer address from being expelled from a register, and a memory device. According to the present... |
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Title | Memory device and method for controlling row hammer |
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