ESD ESD protection circuit with low trigger voltage and high holding voltage characteristics using zener breakdown

An ESD protection circuit with low trigger voltage and high holding voltage characteristics using Zener breakdown is provided. A protection circuit according to an embodiment of the present invention uses Zener breakdown to lower a trigger voltage, blocks the current pass of a surface after the Zene...

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Bibliographic Details
Main Authors CHO KANG IL, LEE SUNG HO, KIM JONG MIN, SONG BO BAE
Format Patent
LanguageEnglish
Korean
Published 26.05.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:An ESD protection circuit with low trigger voltage and high holding voltage characteristics using Zener breakdown is provided. A protection circuit according to an embodiment of the present invention uses Zener breakdown to lower a trigger voltage, blocks the current pass of a surface after the Zener breakdown, improves tolerance characteristics by reducing local temperature, and improves a holding voltage through Zener diode clamping voltage, self-gate biasing, and parasitic NPN base current gain reduction using a floating N+/P+ diffusion region. 제너 항복을 이용한 낮은 트리거 전압과 높은 홀딩 전압 특성을 갖는 ESD 보호회로가 제공된다. 본 발명의 실시예에 따른 보호회로는, 제너 항복을 이용하여 트리거 전압을 낮추고, 제너 항복 이후 표면의 전류 패스를 차단하여 국부적인 온도 감소로 감내 특성을 향상시키며, 제너 다이오드 클램핑 전압과 셀프 게이트 바이어싱 및 플로팅 N+/P+ 확산영역을 이용한 기생 NPN 베이스 전류이득 감소를 통해 홀딩 전압을 향상시킨다.
Bibliography:Application Number: KR20210160179