EFUSE INSIDE AND GATE STRUCTURE ON TRIPLE-WELL REGION

The present disclosure relates to semiconductor structures and, more particularly, to a triple-well phase eFuse and gate structure and a manufacturing method. The structure may include: a substrate including a bounded region; a gate structure formed within the bounded region; and an eFuse formed in...

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Bibliographic Details
Main Authors GAUTHIER ROBERT J. JR, LOISEAU ALAIN F, GINAWI AHMED Y, ABOU KHALIL MICHEL J, SHANK STEVEN M, GEBRESELASIE EPHREM G
Format Patent
LanguageEnglish
Korean
Published 30.03.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The present disclosure relates to semiconductor structures and, more particularly, to a triple-well phase eFuse and gate structure and a manufacturing method. The structure may include: a substrate including a bounded region; a gate structure formed within the bounded region; and an eFuse formed in the bounded region and electrically connected to the gate structure. 본 개시 내용은 반도체 구조물들에 관한 것으로, 더 구체적으로는, 삼중-웰 상의 이퓨즈와 게이트 구조물 및 제조 방법에 관한 것이다. 구조물은 경계진 영역을 포함하는 기판; 경계진 영역 내에 형성된 게이트 구조물; 및 경계진 영역 내에 형성되고 게이트 구조물에 전기적으로 연결된 이퓨즈를 포함한다.
Bibliography:Application Number: KR20220106063