ESD ESD protection circuit with improved characteristics using recombination of electrons and holes and self-gate biasing

• Main Authors: KIM BYUNG SOO, SONG BO BAE, HWANG TAE HO
• Format: Patent
• Language: English; Korean
• Published: 29.11.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Provided is an ESD protection circuit with improved characteristics using recombination of electrons and holes and self-gate biasing. A protection circuit according to an embodiment of the present invention comprises: an N-well connected to an anode; a P-well connected to a cathode; a floating P+ diffusion region which is formed in the N-well and recombines with electrons which have moved to the surface of the N-well after avalanche breakdown has occurred; and a floating N+ diffusion region which is formed in the P-well and recombines with holes which have moved to the surface after the avalanche breakdown has occurred. Accordingly, high temperature tolerance characteristics and high holding voltage characteristics are provided. 전자 및 정공의 재결합 및 셀프 게이트 바이어싱을 이용하여 특성을 향상시킨 ESD 보호회로가 제공된다. 본 발명의 실시예에 따른 보호회로는, 애노드에 연결되는 N-well, 캐소드에 연결되는 P-well, N-well에 형성되며 애벌런치 항복이 발생된 이후에 N-well의 표면으로 이동한 전자와 재결합하는 플로팅 P+ 확산 영역 및 P-well에 형성되며 애벌런치 항복이 발생된 이후에 표면으로 이동한 정공과 재결합하는 플로팅 N+ 확산 영역을 포함한다. 이에 의해, 높은 온도 감내 특성과 높은 홀딩 전압 특성을 갖게 된다.