Single crystal semiconductor structure and method of manufacturing the same

• Main Authors: HAN, JOO HUN, MATIAS VLADIMIR, CHOI, JUN HEE
• Format: Patent
• Language: English; Korean
• Published: 15.09.2022
• Subjects: AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUSPOLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR; BASIC ELECTRIC ELEMENTS; CHEMISTRY; CRYSTAL GROWTH; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; METALLURGY; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITHDEFINED STRUCTURE; REFINING BY ZONE-MELTING OF MATERIAL; SEMICONDUCTOR DEVICES; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITHDEFINED STRUCTURE; SINGLE-CRYSTAL-GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL ORUNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL

A single crystal semiconductor structure and a manufacturing method thereof are disclosed. The disclosed single crystal semiconductor structure comprises: an amorphous substrate; a strain compensation layer disposed under the amorphous substrate; a lattice matched layer disposed above the amorphous substrate and having a single crystal layer structure of two or more layers; and a single crystal semiconductor layer disposed on the lattice matched layer, wherein the lattice matched layer includes a direction control thin film disposed above the amorphous substrate and having a single crystal structure, and a buffer layer made of a material different from the direction control thin film, disposed above the direction control thin film and having a single crystal structure. The direction control thin film is a single crystal thin film, and the thickness of the direction control film is greater than 0 nanometer, but less than or equal to ten times of a critical thickness. The single crystal semiconductor structure can compensate strain due to a difference in thermal expansion coefficients between the amorphous substrate and the single crystal semiconductor layer. 단결정 반도체 구조체 및 그 제조 방법이 개시된다. 개시된 단결정 반도체 구조체는 비정질 기판; 상기 비정질 기판의 하부에 배치된 스트레인 보상층; 상기 비정질 기판의 상부에 배치되며 2층 이상의 단결정 층 구조를 갖는 격자 정합층; 및 상기 격자 정합층 위에 배치된 단결정 반도체층;을 포함하며, 상기 격자 정합층은 상기 비정질 기판의 상부에 배치되며 단결정 구조를 갖는 방향 제어 박막, 및 상기 방향 제어 박막과 상이한 재료로 이루어지며 상기 방향 제어 박막 위에 배치되며 단결정 구조를 갖는 버퍼층을 포함하고, 방향 제어 박막은 단결정 박막이고, 방향 제어 박막의 두께는 0 나노미터(nm)보다 크되, 임계 두께의 열배와 같거나 그보다 작다.