SEMICONDUCTOR PACKAGING AND METHODS OF FORMING SAME

A package includes: a first semiconductor substrate; an integrated circuit die bonded to the first semiconductor substrate using a dielectric-dielectric bond; a molding compound on the first semiconductor substrate and around the integrated circuit die; and a redistribution structure on the first se...

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Bibliographic Details
Main Authors CHEN HSIEN WEI, CHEN MING FA
Format Patent
LanguageEnglish
Korean
Published 29.07.2022
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A package includes: a first semiconductor substrate; an integrated circuit die bonded to the first semiconductor substrate using a dielectric-dielectric bond; a molding compound on the first semiconductor substrate and around the integrated circuit die; and a redistribution structure on the first semiconductor substrate and the integrated circuit die. The redistribution structure is electrically connected to the integrated circuit die. The integrated circuit die includes a second semiconductor substrate. The second semiconductor substrate includes a first sidewall, a second sidewall, and a third sidewall opposite to the first sidewall and the second sidewall. The second sidewall is offset from the first sidewall. 패키지는 제 1 반도체 기판; 유전체-유전체 본드를 이용하여 제 1 반도체 기판에 본딩된 집적 회로 다이; 제 1 반도체 기판 위의 그리고 집적 회로 다이 주위의 몰딩 화합물; 및 제 1 반도체 기판 및 집적 회로 다이 위의 재배선 구조물을 포함하고, 재배선 구조물은 집적 회로 다이에 전기적으로 접속된다. 집적 회로 다이는 제 2 반도체 기판을 포함하고, 제 2 반도체 기판은 제 1 측벽, 제 2 측벽, 및 제 1 측벽 및 제 2 측벽에 대향하는 제 3 측벽을 포함하고, 제 2 측벽은 제 1 측벽으로부터 오프셋된다.
Bibliography:Application Number: KR20210067087