DOUBLE-SIDED CIRCUIT BOARD AND MANUFACTURING METHOD THEROF

The present invention relates to a substrate on which a multi-layered copper foil circuit is formed with an insulating layer interposed therebetween, as a substrate including a pad for mounting a component on one surface (component surface) of the substrate, and a pad (solder pad) for solder joint o...

Full description

Saved in:
Bibliographic Details
Main Authors YOON KWAN SUN, JANG YOUNG JIN, KIM JI HEE
Format Patent
LanguageEnglish
Korean
Published 04.01.2022
Subjects
Online AccessGet full text

Cover

Loading…
Abstract The present invention relates to a substrate on which a multi-layered copper foil circuit is formed with an insulating layer interposed therebetween, as a substrate including a pad for mounting a component on one surface (component surface) of the substrate, and a pad (solder pad) for solder joint on the opposite surface (solder surface) of the substrate. The solder surface has a cavity for embedding and mounting a component, and a pad for flip-chip mounting a component is formed on the bottom surface of the cavity. A cavity material around the cavity has a via hole to connect a copper foil circuit at a cavity bottom level and the solder pad. 본 발명은 절연층을 사이에 두고 다층의 동박회로가 형성된 기판에 있어서, 기판의 일면( 콤포넌트 면 ) 표면에는 부품을 실장하기 위한 패드를 구비하고, 기판의 반대면( 솔더면 ) 표면에는 솔더접합을 위한 패드( 솔더패드 )를 구비한 회로기판으로서, 솔더면은 부품을 매립 실장할 캐비티를 구비하고, 캐비티의 바닥면에는 부품을 플립칩 실장할 패드가 형성되어 있고, 캐비티 주위의 캐비티자재는 비아홀을 구비해서 캐비티 바닥면 레벨의 동박회로와 솔더패드를 연결하는 것을 특징으로 양면 실장용 회로기판을 제공한다.
AbstractList The present invention relates to a substrate on which a multi-layered copper foil circuit is formed with an insulating layer interposed therebetween, as a substrate including a pad for mounting a component on one surface (component surface) of the substrate, and a pad (solder pad) for solder joint on the opposite surface (solder surface) of the substrate. The solder surface has a cavity for embedding and mounting a component, and a pad for flip-chip mounting a component is formed on the bottom surface of the cavity. A cavity material around the cavity has a via hole to connect a copper foil circuit at a cavity bottom level and the solder pad. 본 발명은 절연층을 사이에 두고 다층의 동박회로가 형성된 기판에 있어서, 기판의 일면( 콤포넌트 면 ) 표면에는 부품을 실장하기 위한 패드를 구비하고, 기판의 반대면( 솔더면 ) 표면에는 솔더접합을 위한 패드( 솔더패드 )를 구비한 회로기판으로서, 솔더면은 부품을 매립 실장할 캐비티를 구비하고, 캐비티의 바닥면에는 부품을 플립칩 실장할 패드가 형성되어 있고, 캐비티 주위의 캐비티자재는 비아홀을 구비해서 캐비티 바닥면 레벨의 동박회로와 솔더패드를 연결하는 것을 특징으로 양면 실장용 회로기판을 제공한다.
Author KIM JI HEE
YOON KWAN SUN
JANG YOUNG JIN
Author_xml – fullname: YOON KWAN SUN
– fullname: JANG YOUNG JIN
– fullname: KIM JI HEE
BookMark eNrjYmDJy89L5WSwcvEPdfJx1Q32dHF1UXD2DHIO9QxRcPJ3DHJRcPRzUfB19At1c3QOCQ3y9HNX8HUN8fB3UQjxcA3yd-NhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfHeQUYGRkYGQGBiZuhoTJwqAE3cK1k
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
DocumentTitleAlternate 양면 실장용 회로기판 및 제조방법
ExternalDocumentID KR20220000461A
GroupedDBID EVB
ID FETCH-epo_espacenet_KR20220000461A3
IEDL.DBID EVB
IngestDate Fri Jul 19 14:50:59 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
Korean
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_KR20220000461A3
Notes Application Number: KR20200078132
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220104&DB=EPODOC&CC=KR&NR=20220000461A
ParticipantIDs epo_espacenet_KR20220000461A
PublicationCentury 2000
PublicationDate 20220104
PublicationDateYYYYMMDD 2022-01-04
PublicationDate_xml – month: 01
  year: 2022
  text: 20220104
  day: 04
PublicationDecade 2020
PublicationYear 2022
RelatedCompanies DAEDUCK ELECTRONICS. CO., LTD
RelatedCompanies_xml – name: DAEDUCK ELECTRONICS. CO., LTD
Score 3.3521495
Snippet The present invention relates to a substrate on which a multi-layered copper foil circuit is formed with an insulating layer interposed therebetween, as a...
SourceID epo
SourceType Open Access Repository
SubjectTerms CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
Title DOUBLE-SIDED CIRCUIT BOARD AND MANUFACTURING METHOD THEROF
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220104&DB=EPODOC&locale=&CC=KR&NR=20220000461A
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_mFPVNp-LHlIDSt-LaZtkmDGmTlM7ZdtRW9jbWpQNRtuEq_vsmcdM97S3JwXEJXO4j97sA3DWlXXCw6JgWIW0TYzs3xy0ZpTSE8t5xYdlTBRQOIxJk-GnYHFbgY42F0X1Cv3VzRKlRE6nvpb6vF_9JLKZrK5f3-Ztcmj_6aZcZq-jYVm-72GBelw9iFlOD0m4_MaLkl6ahkpa7A7vKkVad9vmrp3Api02j4h_B3kDym5XHUHmf1-CArv9eq8F-uHrylsOV9i1P4IHFmffMzZce4wzRXkKzXoq82E0YciOGQjfKfJemmapwQCFPg5ihNOBJ7J_Crc9TGphSiNHfnkf9ZFNi5wyqs_msOAckWk5rak2tnBQy2JDhgbCIIB27LciEiIZ9AfVtnC63k6_gUE11jgHXoVp-fhXX0uqW-Y0-rB8oBX21
link.rule.ids 230,309,786,891,25594,76903
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3fS8MwED7mFOebTsUfUwNK34prl6WbMKRNWlq3tqOmsrdhlw5E2Yar-O-bxk33tLeQg-MSuFy-u3wXgLu2jAstLLq6QUhHx9jM9FdLopSmKG_vODfMaUkUDiPip_hp1B5V4GPNhVF9Qr9Vc0TpURPp74U6rxf_SSym3lYu77M3OTV_9HiPaSt0bJa1Xawxp-cOYxZTjdJeP9Gi5FemqJKGvQO7lgSFCiy9OCUvZbEZVLxD2BtKfbPiCCrv8zrU6PrvtTrsh6uStxyuvG95DA8sTp2Bqz8HzGWIBglNA46c2E4YsiOGQjtKPZvytHzhgEKX-zFD3HeT2DuBW8_l1NelEeO_NY_7yabFrVOozuaz_AyQsFrW1JgaGckl2JDwQBhEkK7ZEWRCRNM8h8Y2TRfbxTdQ83k4GA-CqH8JB6VI5RtwA6rF51d-JSNwkV2rjfsBLfOAnw
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=DOUBLE-SIDED+CIRCUIT+BOARD+AND+MANUFACTURING+METHOD+THEROF&rft.inventor=YOON+KWAN+SUN&rft.inventor=JANG+YOUNG+JIN&rft.inventor=KIM+JI+HEE&rft.date=2022-01-04&rft.externalDBID=A&rft.externalDocID=KR20220000461A