ESD PROTECTION CIRCUIT FOR IO BUFFER
The present invention relates to an ESD protection circuit for an IO buffer and, more specifically, to an ESD protection circuit capable of, when an ESD pulse is applied, radiating an ESD surge applied to a pad to a diode but also to a channel current, and improving efficiency of a device used for p...
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Format | Patent |
Language | English Korean |
Published |
14.09.2021
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Abstract | The present invention relates to an ESD protection circuit for an IO buffer and, more specifically, to an ESD protection circuit capable of, when an ESD pulse is applied, radiating an ESD surge applied to a pad to a diode but also to a channel current, and improving efficiency of a device used for protecting the ESD. The ESD protection circuit comprises: a floating N well bias circuit connected to a pad of an IO driver for setting an output voltage based on an IO voltage; a switch circuit connected to a node connecting an IO logic to an IO driver and switching the connection between the IO logic and the IO driver based on the IO voltage; and a pull-down circuit connected to another node connecting the IO logic and the IO driver and setting a voltage applied to the IO driver based on the IO voltage.
본 발명은 입출력 버퍼를 위한 ESD 보호 회로에 관한 것으로, 더욱 상세하게는 ESD 펄스가 인가되면 패드에 인가된 ESD 서지(Surge)를 다이오드뿐만 아니라 채널 전류로도 방사시켜 ESD 보호를 위해 사용되는 소자의 효율성을 향상시키도록 하는 ESD 보호 회로에 관한 것이다. 상기 ESD 보호 회로는 IO 드라이버의 패드와 연결되고, 입출력 전압을 근거로 출력 전압을 설정하는 플로팅 N 웰 바이어스 회로, IO 로직과 IO 드라이버를 연결하는 노드에 연결되고, 입출력 전압을 근거로 IO 로직과 IO 드라이버의 연결을 스위칭하는 스위치 회로 및 IO 로직과 IO 드라이버를 연결하는 다른 노드에 연결되고, 입출력 전압을 근거로 IO 드라이버로 인가되는 전압을 설정하는 풀 다운 회로를 포함한다. |
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AbstractList | The present invention relates to an ESD protection circuit for an IO buffer and, more specifically, to an ESD protection circuit capable of, when an ESD pulse is applied, radiating an ESD surge applied to a pad to a diode but also to a channel current, and improving efficiency of a device used for protecting the ESD. The ESD protection circuit comprises: a floating N well bias circuit connected to a pad of an IO driver for setting an output voltage based on an IO voltage; a switch circuit connected to a node connecting an IO logic to an IO driver and switching the connection between the IO logic and the IO driver based on the IO voltage; and a pull-down circuit connected to another node connecting the IO logic and the IO driver and setting a voltage applied to the IO driver based on the IO voltage.
본 발명은 입출력 버퍼를 위한 ESD 보호 회로에 관한 것으로, 더욱 상세하게는 ESD 펄스가 인가되면 패드에 인가된 ESD 서지(Surge)를 다이오드뿐만 아니라 채널 전류로도 방사시켜 ESD 보호를 위해 사용되는 소자의 효율성을 향상시키도록 하는 ESD 보호 회로에 관한 것이다. 상기 ESD 보호 회로는 IO 드라이버의 패드와 연결되고, 입출력 전압을 근거로 출력 전압을 설정하는 플로팅 N 웰 바이어스 회로, IO 로직과 IO 드라이버를 연결하는 노드에 연결되고, 입출력 전압을 근거로 IO 로직과 IO 드라이버의 연결을 스위칭하는 스위치 회로 및 IO 로직과 IO 드라이버를 연결하는 다른 노드에 연결되고, 입출력 전압을 근거로 IO 드라이버로 인가되는 전압을 설정하는 풀 다운 회로를 포함한다. |
Author | KIM SEUNG HOO LEE SANG MOK CHA JAE AH JANG JOON TAE |
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Snippet | The present invention relates to an ESD protection circuit for an IO buffer and, more specifically, to an ESD protection circuit capable of, when an ESD pulse... |
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SubjectTerms | BASIC ELECTRONIC CIRCUITRY CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRICITY EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS GENERATION PULSE TECHNIQUE |
Title | ESD PROTECTION CIRCUIT FOR IO BUFFER |
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