SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

The present invention relates to a semiconductor memory device and a manufacturing method thereof and, more specifically, to an element isolation film included between a pass gate and a main gate in a buried cell array transistor (BCAT) structure. The semiconductor memory device comprises: a substra...

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Main Authors KIM JUN SOO, CHAE KYO SUK, LEE TAE YOON, MOON DAE HYUN
Format Patent
LanguageEnglish
Korean
Published 23.11.2020
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Abstract The present invention relates to a semiconductor memory device and a manufacturing method thereof and, more specifically, to an element isolation film included between a pass gate and a main gate in a buried cell array transistor (BCAT) structure. The semiconductor memory device comprises: a substrate; a first element isolation film formed in the substrate; a first gate structure extended in a first direction in the first element isolation film; a second gate structure spaced apart from the first gate structure in a second direction; and a second element isolation film disposed on a sidewall of the first element isolation film. The first and second gate structures each include first and second gate electrodes, and the sidewall of the first element isolation film includes a first portion, a second portion on the first portion, and a third portion on the second portion. The second element isolation film is disposed on the second portion, and the second element isolation film overlaps the first and second gate electrodes in the second direction. The second element isolation film protrudes from the second portion in the second direction, and the first direction and the second direction cross each other. 본 발명은 반도체 메모리 장치 및 그 제조 방법에 관한 것으로, 좀 더 구체적으로, 매립 셀 어레이 트랜지스터(BCAT; buried cell array transistor) 구조에서, 패스 게이트(pass gate)와 메인 게이트(main gate) 사이에 포함되는 소자 분리막에 관한 것이다. 본 발명의 반도체 메모리 장치는, 기판, 기판 내에 형성된 제1 소자 분리막, 제1 소자 분리막 내에, 제1 방향으로 연장되는 제1 게이트 구조체, 제1 게이트 구조체와 제2 방향으로 이격된 제2 게이트 구조체 및 제1 소자 분리막의 측벽에 배치되는 제2 소자 분리막을 포함하되, 제1 및 제2 게이트 구조체는 각각 제1 및 제2 게이트 전극을 포함하고, 제1 소자 분리막의 측벽은 제1 부분과, 제1 부분 상의 제2 부분과, 제2 부분 상의 제3 부분을 포함하고, 제2 소자 분리막은 제2 부분에 배치되고, 제2 소자 분리막은 제1 및 제2 게이트 전극과 제2 방향으로 중첩되고, 제2 소자 분리막은 제2 부분으로부터 제2 방향으로 돌출되고, 제1 방향 및 제2 방향은 서로 교차한다.
AbstractList The present invention relates to a semiconductor memory device and a manufacturing method thereof and, more specifically, to an element isolation film included between a pass gate and a main gate in a buried cell array transistor (BCAT) structure. The semiconductor memory device comprises: a substrate; a first element isolation film formed in the substrate; a first gate structure extended in a first direction in the first element isolation film; a second gate structure spaced apart from the first gate structure in a second direction; and a second element isolation film disposed on a sidewall of the first element isolation film. The first and second gate structures each include first and second gate electrodes, and the sidewall of the first element isolation film includes a first portion, a second portion on the first portion, and a third portion on the second portion. The second element isolation film is disposed on the second portion, and the second element isolation film overlaps the first and second gate electrodes in the second direction. The second element isolation film protrudes from the second portion in the second direction, and the first direction and the second direction cross each other. 본 발명은 반도체 메모리 장치 및 그 제조 방법에 관한 것으로, 좀 더 구체적으로, 매립 셀 어레이 트랜지스터(BCAT; buried cell array transistor) 구조에서, 패스 게이트(pass gate)와 메인 게이트(main gate) 사이에 포함되는 소자 분리막에 관한 것이다. 본 발명의 반도체 메모리 장치는, 기판, 기판 내에 형성된 제1 소자 분리막, 제1 소자 분리막 내에, 제1 방향으로 연장되는 제1 게이트 구조체, 제1 게이트 구조체와 제2 방향으로 이격된 제2 게이트 구조체 및 제1 소자 분리막의 측벽에 배치되는 제2 소자 분리막을 포함하되, 제1 및 제2 게이트 구조체는 각각 제1 및 제2 게이트 전극을 포함하고, 제1 소자 분리막의 측벽은 제1 부분과, 제1 부분 상의 제2 부분과, 제2 부분 상의 제3 부분을 포함하고, 제2 소자 분리막은 제2 부분에 배치되고, 제2 소자 분리막은 제1 및 제2 게이트 전극과 제2 방향으로 중첩되고, 제2 소자 분리막은 제2 부분으로부터 제2 방향으로 돌출되고, 제1 방향 및 제2 방향은 서로 교차한다.
Author KIM JUN SOO
MOON DAE HYUN
CHAE KYO SUK
LEE TAE YOON
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Snippet The present invention relates to a semiconductor memory device and a manufacturing method thereof and, more specifically, to an element isolation film included...
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SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
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