POWER AMPLIFIER APPARATUS
A power amplifying device capable of suppressing variations in operation of a plurality of transistors is provided. A power amplifying device includes: a semiconductor substrate; a plurality of first transistors installed on the semiconductor substrate; a plurality of second transistors; a collector...
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Main Authors | , , , , , , |
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Format | Patent |
Language | English Korean |
Published |
14.10.2020
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Abstract | A power amplifying device capable of suppressing variations in operation of a plurality of transistors is provided. A power amplifying device includes: a semiconductor substrate; a plurality of first transistors installed on the semiconductor substrate; a plurality of second transistors; a collector terminal electrically connected to collectors of the plurality of first transistors; a first inductor having one end electrically connected to the collector terminal and the other end electrically connected to a power supply potential; an emitter terminal electrically connected to emitters of the plurality of second transistors and adjacent to the collector terminal in a second direction; a second inductor having one end electrically connected to the emitter terminal and the other end electrically connected to a reference potential; capacitor having one end electrically connected to the collectors of the plurality of first transistors and the other end electrically connected to the emitters of the plurality of second transistors.
[과제] 복수의 트랜지스터의 동작의 편차를 억제할 수 있는 전력 증폭 장치를 제공한다. [해결 수단] 전력 증폭 장치는 반도체 기판과, 반도체 기판 상에 설치된 복수의 제 1 트랜지스터와, 복수의 제 2 트랜지스터와, 복수의 제 1 트랜지스터의 컬렉터에 전기적으로 접속된 컬렉터 단자와, 일단측이 컬렉터 단자에 전기적으로 접속되고, 타단측이 전원 전위에 전기적으로 접속된 제 1 인덕터와, 복수의 제 2 트랜지스터의 이미터에 전기적으로 접속되고, 컬렉터 단자와 제 2 방향으로 이웃하여 설치된 이미터 단자와, 일단측이 이미터 단자에 전기적으로 접속되고, 타단측이 기준 전위에 전기적으로 접속된 제 2 인덕터와, 일단측이 복수의 제 1 트랜지스터의 컬렉터에 전기적으로 접속되고, 타단측이 복수의 제 2 트랜지스터의 이미터에 전기적으로 접속된 콘덴서를 갖는다. |
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AbstractList | A power amplifying device capable of suppressing variations in operation of a plurality of transistors is provided. A power amplifying device includes: a semiconductor substrate; a plurality of first transistors installed on the semiconductor substrate; a plurality of second transistors; a collector terminal electrically connected to collectors of the plurality of first transistors; a first inductor having one end electrically connected to the collector terminal and the other end electrically connected to a power supply potential; an emitter terminal electrically connected to emitters of the plurality of second transistors and adjacent to the collector terminal in a second direction; a second inductor having one end electrically connected to the emitter terminal and the other end electrically connected to a reference potential; capacitor having one end electrically connected to the collectors of the plurality of first transistors and the other end electrically connected to the emitters of the plurality of second transistors.
[과제] 복수의 트랜지스터의 동작의 편차를 억제할 수 있는 전력 증폭 장치를 제공한다. [해결 수단] 전력 증폭 장치는 반도체 기판과, 반도체 기판 상에 설치된 복수의 제 1 트랜지스터와, 복수의 제 2 트랜지스터와, 복수의 제 1 트랜지스터의 컬렉터에 전기적으로 접속된 컬렉터 단자와, 일단측이 컬렉터 단자에 전기적으로 접속되고, 타단측이 전원 전위에 전기적으로 접속된 제 1 인덕터와, 복수의 제 2 트랜지스터의 이미터에 전기적으로 접속되고, 컬렉터 단자와 제 2 방향으로 이웃하여 설치된 이미터 단자와, 일단측이 이미터 단자에 전기적으로 접속되고, 타단측이 기준 전위에 전기적으로 접속된 제 2 인덕터와, 일단측이 복수의 제 1 트랜지스터의 컬렉터에 전기적으로 접속되고, 타단측이 복수의 제 2 트랜지스터의 이미터에 전기적으로 접속된 콘덴서를 갖는다. |
Author | TERASHIMA TOSHIKAZU ITOU MAKOTO ARAYASHIKI SATOSHI HARIMA FUMIO TANAKA SATOSHI YOSHIDA CHIKARA WATANABE KAZUO |
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Snippet | A power amplifying device capable of suppressing variations in operation of a plurality of transistors is provided. A power amplifying device includes: a... |
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Title | POWER AMPLIFIER APPARATUS |
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