SEMICONDUCTOR DEVICE AND METHOD
In one embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a lateral side of the gate stac...
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Format | Patent |
Language | English Korean |
Published |
04.05.2020
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Abstract | In one embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a lateral side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, wherein the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.
일 실시예에서, 디바이스는: 기판으로부터 연장되는 제1 핀; 제1 핀 상에 배치된 게이트 스택; 제1 핀 내에 배치된 소스/드레인 영역; 소스/드레인 영역 위에 배치된 콘택트 에칭 스톱 층(CESL); 게이트 스택의 측면을 따라서 연장되는 게이트 스페이서; 및 CESL과 게이트 스페이서 사이에 배치된 유전체 플러그를 포함하고, 여기서 유전체 플러그, CESL, 게이트 스페이서, 및 소스/드레인 영역은 집합적으로 게이트 스택을 소스/드레인 영역으로부터 물리적으로 분리시키는 보이드를 규정한다. |
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AbstractList | In one embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a lateral side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, wherein the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.
일 실시예에서, 디바이스는: 기판으로부터 연장되는 제1 핀; 제1 핀 상에 배치된 게이트 스택; 제1 핀 내에 배치된 소스/드레인 영역; 소스/드레인 영역 위에 배치된 콘택트 에칭 스톱 층(CESL); 게이트 스택의 측면을 따라서 연장되는 게이트 스페이서; 및 CESL과 게이트 스페이서 사이에 배치된 유전체 플러그를 포함하고, 여기서 유전체 플러그, CESL, 게이트 스페이서, 및 소스/드레인 영역은 집합적으로 게이트 스택을 소스/드레인 영역으로부터 물리적으로 분리시키는 보이드를 규정한다. |
Author | SIE MING JHE CHEN RYAN CHIA JEN YIN LI WEI WANG SHIANG BAU HUANG CHEN HUANG |
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RelatedCompanies | TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD |
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Snippet | In one embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the... |
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SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | SEMICONDUCTOR DEVICE AND METHOD |
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