Variable resistance memory Device and method of forming the same
According to embodiments of the present invention, a method of manufacturing a variable resistance memory device comprises the steps of: forming an array of memory cells on a substrate, each memory cell including a variable resistance structure and a switching element; and forming a sidewall insulat...
Saved in:
Main Authors | , , , , |
---|---|
Format | Patent |
Language | English Korean |
Published |
17.04.2020
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | According to embodiments of the present invention, a method of manufacturing a variable resistance memory device comprises the steps of: forming an array of memory cells on a substrate, each memory cell including a variable resistance structure and a switching element; and forming a sidewall insulating layer covering a sidewall of the switching element. The forming the sidewall insulating layer includes: a main step of performing multiple times of supplying a silicon source and supplying a reactive gas in one cycle; and a preliminary step of supplying the silicon source to an exposed sidewall of the switching element before the main step. A time duration to supply the silicon source in the preliminary step is longer than one cycle in the main step.
본 발명의 실시예들에 따른 가변 저항 메모리 소자의 제조 방법은 기판 상에 2차원적으로 배열되고 각각 가변 저항 구조체 및 스위칭 소자를 포함하는 메모리 셀들의 어레이를 형성하는 것 및 상기 스위칭 소자의 측벽을 덮는 측벽 절연막을 형성하는 것을 포함한다. 상기 측벽 절연막을 형성하는 것은 실리콘 소스 공급 및 반응 가스 공급을 하나의 사이클로 하여 복수 회 수행하는 메인 단계 및 상기 메인 단계의 시작 이전에, 노출된 상기 스위칭 소자의 측벽에 상기 실리콘 소스를 공급하는 예비 단계를 포함한다. 상기 예비 단계의 상기 실리콘 소스의 공급 시간은 상기 메인 단계의 한 사이클보다 길다. |
---|---|
AbstractList | According to embodiments of the present invention, a method of manufacturing a variable resistance memory device comprises the steps of: forming an array of memory cells on a substrate, each memory cell including a variable resistance structure and a switching element; and forming a sidewall insulating layer covering a sidewall of the switching element. The forming the sidewall insulating layer includes: a main step of performing multiple times of supplying a silicon source and supplying a reactive gas in one cycle; and a preliminary step of supplying the silicon source to an exposed sidewall of the switching element before the main step. A time duration to supply the silicon source in the preliminary step is longer than one cycle in the main step.
본 발명의 실시예들에 따른 가변 저항 메모리 소자의 제조 방법은 기판 상에 2차원적으로 배열되고 각각 가변 저항 구조체 및 스위칭 소자를 포함하는 메모리 셀들의 어레이를 형성하는 것 및 상기 스위칭 소자의 측벽을 덮는 측벽 절연막을 형성하는 것을 포함한다. 상기 측벽 절연막을 형성하는 것은 실리콘 소스 공급 및 반응 가스 공급을 하나의 사이클로 하여 복수 회 수행하는 메인 단계 및 상기 메인 단계의 시작 이전에, 노출된 상기 스위칭 소자의 측벽에 상기 실리콘 소스를 공급하는 예비 단계를 포함한다. 상기 예비 단계의 상기 실리콘 소스의 공급 시간은 상기 메인 단계의 한 사이클보다 길다. |
Author | KO YOUNG MIN CHOI DONGSUNG KIM JONGUK KIM BYONGJU JUNG JAEHO |
Author_xml | – fullname: KIM JONGUK – fullname: CHOI DONGSUNG – fullname: KIM BYONGJU – fullname: KO YOUNG MIN – fullname: JUNG JAEHO |
BookMark | eNrjYmDJy89L5WRwCEssykxMyklVKEotziwuScxLTlXITc3NL6pUcEktywTyEvNSgCIlGfkpCvlpCmn5RbmZeekKJRmpCsWJuak8DKxpiTnFqbxQmptB2c01xNlDN7UgPz61uCAxOTUvtSTeO8jIwMjAwMDY0sLC1NGYOFUAg58zjQ |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
DocumentTitleAlternate | 가변 저항 메모리 소자 및 이의 제조 방법 |
ExternalDocumentID | KR20200039885A |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_KR20200039885A3 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 12:59:38 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English Korean |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_KR20200039885A3 |
Notes | Application Number: KR20180119096 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200417&DB=EPODOC&CC=KR&NR=20200039885A |
ParticipantIDs | epo_espacenet_KR20200039885A |
PublicationCentury | 2000 |
PublicationDate | 20200417 |
PublicationDateYYYYMMDD | 2020-04-17 |
PublicationDate_xml | – month: 04 year: 2020 text: 20200417 day: 17 |
PublicationDecade | 2020 |
PublicationYear | 2020 |
RelatedCompanies | SAMSUNG ELECTRONICS CO., LTD |
RelatedCompanies_xml | – name: SAMSUNG ELECTRONICS CO., LTD |
Score | 3.2345629 |
Snippet | According to embodiments of the present invention, a method of manufacturing a variable resistance memory device comprises the steps of: forming an array of... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | Variable resistance memory Device and method of forming the same |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200417&DB=EPODOC&locale=&CC=KR&NR=20200039885A |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1bS8MwFD7MKeqbTsXLlIDSt2LvrQ9FXS8Mxy6UOfY2mi4F0bXDVsR_7zldp3vaW5NASBO-fOck-c4BuEsMS-Fxqss656lscCFk5BlFNnlqqsgHuqOR3rk_sLqvxsvUnDbgY62FqeKEflfBERFRCeK9rPbr5f8hll-9rSzu-RtW5Y_h2PWl2jumJVdtye-4wWjoDz3J89xeJA2iVZuiPziO-bwDu2RIU6T9YNIhXcpyk1TCI9gbYX9ZeQyN97wFB94691oL9vv1lTd-1ugrTuBpgo4tSZ0Y-shk92E1W9BT2R_mC4I8i7M5WyWFZnnKyCBFamJo5LEiXohTuA2DsdeVcSizvz-f9aLNcetn0MzyTJwDSwwS0AqBCNINK7XjxESvmDLpaDHXEuUC2tt6utzefAWHVKRLE9VuQ7P8_BLXyL0lv6mm7BfCUIda |
link.rule.ids | 230,309,786,891,25594,76906 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1NT8JAEJ0gGvGmqPEDdRNNb42lH7QeGpWWpgoFQpBwI926TYzSEltj_PfOlKKcuG12ks3uNq9vZnffDMBNpLcUHsaarHEeyzoXQkaeUWSDx0YT-UCzVNI7B_2W_6I_T41pBT5WWpgiT-h3kRwRERUh3vPif734P8Ryi7eV2S1_w6703hvbrlRGx_TJm6bktu3OcOAOHMlx7O5I6o-WNkW7syzjcQu2TcrPS87TpE26lMU6qXj7sDPE8ZL8ACrvaR1qzqr2Wh12g_LKG5sl-rJDeJhgYEtSJ4YxMvl92M3m9FT2h7mCIM_C5JUti0KzNGbkkCI1MXTyWBbOxRFce52x48s4ldnfymfd0fq8tWOoJmkiToBFOglohUAEaXorNsPIwKiYKumoIVcj5RQam0Y622y-gpo_Dnqz3lO_ew57ZKILlKbZgGr--SUukIdzflls3y8_n4pH |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Variable+resistance+memory+Device+and+method+of+forming+the+same&rft.inventor=KIM+JONGUK&rft.inventor=CHOI+DONGSUNG&rft.inventor=KIM+BYONGJU&rft.inventor=KO+YOUNG+MIN&rft.inventor=JUNG+JAEHO&rft.date=2020-04-17&rft.externalDBID=A&rft.externalDocID=KR20200039885A |