METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
One of objectives of the present invention is to provide a method for manufacturing a semiconductor device with reduced defects in characteristics of the semiconductor device due to cracks. By providing a crack inhibiting layer around a portion where a semiconductor element is formed, generation of...
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| Main Author | |
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| Format | Patent |
| Language | English Korean |
| Published |
19.02.2020
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| Subjects | |
| Online Access | Get full text |
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| Abstract | One of objectives of the present invention is to provide a method for manufacturing a semiconductor device with reduced defects in characteristics of the semiconductor device due to cracks. By providing a crack inhibiting layer around a portion where a semiconductor element is formed, generation of cracks from the outer circumference portion of a substrate is inhibited and damage to the semiconductor element can be reduced. In addition, in case of delamination and displacing, even if a physical force is applied from the outer circumference portion to the semiconductor device, the proceeding (growth) of the cracks can be prevented by the crack inhibiting layer.
본 발명은 크랙에 기인하는 반도체 장치의 특성 불량을 저감한 반도체 장치의 제작 방법을 제공하는 것을 목적 중 하나로 한다. 반도체 소자가 형성되는 주변에 크랙 억지층을 제공함으로써 기판 외주부로부터 크랙이 발생하는 것을 억지하고 반도체 소자에 가해지는 대미지를 저감할 수 있다. 또한, 박리 및 전치할 때, 상기 반도체 장치에 외주부로부터 물리적인 힘이 가해진 경우라도 크랙 억지층에 의하여 상기 반도체 장치까지 크랙이 진행(성장)하는 것을 방지할 수 있다. |
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| AbstractList | One of objectives of the present invention is to provide a method for manufacturing a semiconductor device with reduced defects in characteristics of the semiconductor device due to cracks. By providing a crack inhibiting layer around a portion where a semiconductor element is formed, generation of cracks from the outer circumference portion of a substrate is inhibited and damage to the semiconductor element can be reduced. In addition, in case of delamination and displacing, even if a physical force is applied from the outer circumference portion to the semiconductor device, the proceeding (growth) of the cracks can be prevented by the crack inhibiting layer.
본 발명은 크랙에 기인하는 반도체 장치의 특성 불량을 저감한 반도체 장치의 제작 방법을 제공하는 것을 목적 중 하나로 한다. 반도체 소자가 형성되는 주변에 크랙 억지층을 제공함으로써 기판 외주부로부터 크랙이 발생하는 것을 억지하고 반도체 소자에 가해지는 대미지를 저감할 수 있다. 또한, 박리 및 전치할 때, 상기 반도체 장치에 외주부로부터 물리적인 힘이 가해진 경우라도 크랙 억지층에 의하여 상기 반도체 장치까지 크랙이 진행(성장)하는 것을 방지할 수 있다. |
| Author | CHIDA AKIHIRO |
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| RelatedCompanies | SEMICONDUCTOR ENERGY LABORATORY CO., LTD |
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| Snippet | One of objectives of the present invention is to provide a method for manufacturing a semiconductor device with reduced defects in characteristics of the... |
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| SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| Title | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE |
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