Semiconductor memory device method of driving the same and method of fabricating the same
The present invention relates to a semiconductor memory device, a method of driving the same, and a method of manufacturing the same. A semiconductor memory device according to an embodiment of the present invention is a semiconductor memory device including a plurality of memory cell transistors ar...
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Format | Patent |
Language | English Korean |
Published |
08.10.2019
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Abstract | The present invention relates to a semiconductor memory device, a method of driving the same, and a method of manufacturing the same. A semiconductor memory device according to an embodiment of the present invention is a semiconductor memory device including a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the memory cell transistors may include a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating part defined in the portion of the common semiconductor layer and adjusting the threshold voltage of the memory cell transistor and the conductance of a channel according to a charged state. In addition, the plurality of memory cell transistors provide a memory string connected in series with each other along the common semiconductor layer. The semiconductor memory device can be highly integrated and driven at high speed and low power.
본 발명은 반도체 메모리 소자, 이의 구동 방법 및 이의 제조 방법에 관한 것이다. 본 발명의 일 실시예에 따른 반도체 메모리 소자는, 공통 반도체 층을 따라 배열된 복수의 메모리 셀 트랜지스터들을 포함하는 반도체 메모리 소자이다. 각 메모리 셀 트랜지스터는, 상기 공통 반도체 층에 형성된 제 1 소스/드레인 영역 및 제 2 소스/드레인 영역; 상기 제 1 소스/드레인 영역과 상기 제 2 소스/드레인 영역 사이의 상기 공통 반도체 층의 일부 상에 형성된 게이트 스택; 및 상기 공통 반도체 층의 상기 일부 내에 정의되고 하전 상태에 따라 상기 메모리 셀 트랜지스터의 문턱 전압 및 채널의 컨덕턴스를 조절하는 전기적 플로팅부를 포함할 수 있다. 또한, 상기 복수의 메모리 셀 트랜지스터들은 상기 공통 반도체 층을 따라 서로 직렬 연결된 메모리 스트링을 제공한다. |
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AbstractList | The present invention relates to a semiconductor memory device, a method of driving the same, and a method of manufacturing the same. A semiconductor memory device according to an embodiment of the present invention is a semiconductor memory device including a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the memory cell transistors may include a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating part defined in the portion of the common semiconductor layer and adjusting the threshold voltage of the memory cell transistor and the conductance of a channel according to a charged state. In addition, the plurality of memory cell transistors provide a memory string connected in series with each other along the common semiconductor layer. The semiconductor memory device can be highly integrated and driven at high speed and low power.
본 발명은 반도체 메모리 소자, 이의 구동 방법 및 이의 제조 방법에 관한 것이다. 본 발명의 일 실시예에 따른 반도체 메모리 소자는, 공통 반도체 층을 따라 배열된 복수의 메모리 셀 트랜지스터들을 포함하는 반도체 메모리 소자이다. 각 메모리 셀 트랜지스터는, 상기 공통 반도체 층에 형성된 제 1 소스/드레인 영역 및 제 2 소스/드레인 영역; 상기 제 1 소스/드레인 영역과 상기 제 2 소스/드레인 영역 사이의 상기 공통 반도체 층의 일부 상에 형성된 게이트 스택; 및 상기 공통 반도체 층의 상기 일부 내에 정의되고 하전 상태에 따라 상기 메모리 셀 트랜지스터의 문턱 전압 및 채널의 컨덕턴스를 조절하는 전기적 플로팅부를 포함할 수 있다. 또한, 상기 복수의 메모리 셀 트랜지스터들은 상기 공통 반도체 층을 따라 서로 직렬 연결된 메모리 스트링을 제공한다. |
Author | AHN JIN HONG |
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Snippet | The present invention relates to a semiconductor memory device, a method of driving the same, and a method of manufacturing the same. A semiconductor memory... |
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Title | Semiconductor memory device method of driving the same and method of fabricating the same |
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