METHOD AND APPARATUS FOR REDUCING CAPACITANCE OF INPUT/OUTPUT PINS OF MEMORY DEVICE

In one embodiment of the present invention, an apparatus comprises: a tier including alternated first and second layers, wherein the first layers include first conductive materials and the second layers include second conductive materials; a lower metal layer located on the lower side of the tier; a...

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Bibliographic Details
Main Authors ZHU HONGBIN, HALLER GORDON A, DAVIS JAMES E, CARLSON MERRI LYN, VIOLETTE MICHAEL P, MATHEW JAMES, DUESMAN KEVIN G
Format Patent
LanguageEnglish
Korean
Published 27.12.2018
Subjects
ELECTRICITY
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Summary:In one embodiment of the present invention, an apparatus comprises: a tier including alternated first and second layers, wherein the first layers include first conductive materials and the second layers include second conductive materials; a lower metal layer located on the lower side of the tier; a bond pad located on the upper side of the tier, wherein the bond pad is coupled to the lower metal layer by a via extended after penetrating the tier; and a first channel formed to penetrate a part of the tier, wherein the first channel surrounds the via and includes second dielectric materials. 일 실시예에서, 장치는 교대로 있는 제1 및 제2 층들을 포함하는 티어 - 제1 층들은 제1 전도성 재료를 포함하고 제2 층들은 제1 유전체 재료를 포함함 -; 티어 아래쪽에 있는 하부 금속 층; 티어 위쪽에 있는 본드 패드 - 본드 패드는 티어를 관통하여 연장되는 비아에 의해 하부 금속 층에 결합됨 -; 및 티어의 일부분을 관통하게 형성된 제1 채널 - 제1 채널은 비아를 둘러싸고, 제1 채널은 제2 유전체 재료를 포함함 - 을 포함한다.
Bibliography:Application Number: KR20180056046