Semiconductor memory device

A semiconductor memory device is provided. The semiconductor memory device includes a static random access memory (SRAM) cell, a sensing circuit connected to the SRAM cell through a first bit line and a second bit line different from the first bit line and sensing data stored in the SRAM cell, and a...

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Main Authors SONG, TAE JOONG, JUNG, SEONG OOK, KIM, GYU HONG, RIM, WOO JIN, JEONG, HAN WOOL
Format Patent
LanguageEnglish
Korean
Published 28.02.2017
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Abstract A semiconductor memory device is provided. The semiconductor memory device includes a static random access memory (SRAM) cell, a sensing circuit connected to the SRAM cell through a first bit line and a second bit line different from the first bit line and sensing data stored in the SRAM cell, and a bit line voltage regulating circuit which is connected to the SRAM cell through the first and second bit lines and precharges the first bit line with a first voltage lower than a supply voltage, and precharges the second bit line with a different second voltage. So, read operation speed can be improved. 반도체 메모리 장치가 제공된다. 상기 반도체 메모리 장치는, SRAM(Static Random Access Memory) 셀, 제1 비트라인과 상기 제1 비트라인과 다른 제2 비트라인을 통해 상기 SRAM 셀에 접속되고, 상기 SRAM 셀에 저장된 데이터를 센싱하는 센싱 회로, 및 상기 제1 및 제2 비트라인을 통해 상기 SRAM 셀에 접속되고, 상기 제1 비트라인을 공급전압보다 낮은 제1 전압으로 프리차지하고, 상기 제2 비트라인을 상기 공급전압보다 낮고 상기 제1 전압과 다른 제2 전압으로 프리차지하는 비트라인 전압 조절 회로를 포함한다.
AbstractList A semiconductor memory device is provided. The semiconductor memory device includes a static random access memory (SRAM) cell, a sensing circuit connected to the SRAM cell through a first bit line and a second bit line different from the first bit line and sensing data stored in the SRAM cell, and a bit line voltage regulating circuit which is connected to the SRAM cell through the first and second bit lines and precharges the first bit line with a first voltage lower than a supply voltage, and precharges the second bit line with a different second voltage. So, read operation speed can be improved. 반도체 메모리 장치가 제공된다. 상기 반도체 메모리 장치는, SRAM(Static Random Access Memory) 셀, 제1 비트라인과 상기 제1 비트라인과 다른 제2 비트라인을 통해 상기 SRAM 셀에 접속되고, 상기 SRAM 셀에 저장된 데이터를 센싱하는 센싱 회로, 및 상기 제1 및 제2 비트라인을 통해 상기 SRAM 셀에 접속되고, 상기 제1 비트라인을 공급전압보다 낮은 제1 전압으로 프리차지하고, 상기 제2 비트라인을 상기 공급전압보다 낮고 상기 제1 전압과 다른 제2 전압으로 프리차지하는 비트라인 전압 조절 회로를 포함한다.
Author KIM, GYU HONG
SONG, TAE JOONG
JUNG, SEONG OOK
JEONG, HAN WOOL
RIM, WOO JIN
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Snippet A semiconductor memory device is provided. The semiconductor memory device includes a static random access memory (SRAM) cell, a sensing circuit connected to...
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PHYSICS
STATIC STORES
Title Semiconductor memory device
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