THREAD PAUSE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
According to one aspect of the present invention, a processor includes a decode unit decoding a thread pause instruction from a first thread. A back end part of the processor is connected to the decode unit. The back end part of the processor pauses processes of follow-up instructions of a first thr...
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Main Authors | , , , , , , |
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Format | Patent |
Language | English Korean |
Published |
29.01.2016
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Abstract | According to one aspect of the present invention, a processor includes a decode unit decoding a thread pause instruction from a first thread. A back end part of the processor is connected to the decode unit. The back end part of the processor pauses processes of follow-up instructions of a first thread for execution in response to the thread pause instruction. The follow-up instructions occur after the thread pause instruction in a program sequence. In addition, the processor maintains at least most of the back end part of the processor in a state where the instructions of the first thread except for the thread pause instruction are lacking for a predetermined period of time in response to the thread pause instruction. Most of the back end part of the processor can include a plurality of execution units and an instruction cue unit.
일 양태의 프로세서는 제1 스레드로부터의 스레드 일시중지 명령어를 디코드하는 디코드 유닛을 포함한다. 프로세서의 백 엔드 부분은 디코드 유닛과 연결된다. 프로세서의 백 엔드 부분은, 스레드 일시중지 명령어에 응답하여, 실행을 위한 제1 스레드의 후속 명령어들의 처리를 일시중지한다. 후속 명령어들은 프로그램 순서상 스레드 일시중지 명령어 뒤에 발생한다. 또한, 백 엔드 부분은, 스레드 일시중지 명령어에 응답하여, 미리 결정된 기간 동안, 프로세서의 백 엔드 부분의 적어도 대부분을, 스레드 일시중지 명령어를 제외한 제1 스레드의 명령어들이 결여된 상태로 유지한다. 대부분은 복수의 실행 유닛들 및 명령어 큐 유닛을 포함할 수 있다. |
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AbstractList | According to one aspect of the present invention, a processor includes a decode unit decoding a thread pause instruction from a first thread. A back end part of the processor is connected to the decode unit. The back end part of the processor pauses processes of follow-up instructions of a first thread for execution in response to the thread pause instruction. The follow-up instructions occur after the thread pause instruction in a program sequence. In addition, the processor maintains at least most of the back end part of the processor in a state where the instructions of the first thread except for the thread pause instruction are lacking for a predetermined period of time in response to the thread pause instruction. Most of the back end part of the processor can include a plurality of execution units and an instruction cue unit.
일 양태의 프로세서는 제1 스레드로부터의 스레드 일시중지 명령어를 디코드하는 디코드 유닛을 포함한다. 프로세서의 백 엔드 부분은 디코드 유닛과 연결된다. 프로세서의 백 엔드 부분은, 스레드 일시중지 명령어에 응답하여, 실행을 위한 제1 스레드의 후속 명령어들의 처리를 일시중지한다. 후속 명령어들은 프로그램 순서상 스레드 일시중지 명령어 뒤에 발생한다. 또한, 백 엔드 부분은, 스레드 일시중지 명령어에 응답하여, 미리 결정된 기간 동안, 프로세서의 백 엔드 부분의 적어도 대부분을, 스레드 일시중지 명령어를 제외한 제1 스레드의 명령어들이 결여된 상태로 유지한다. 대부분은 복수의 실행 유닛들 및 명령어 큐 유닛을 포함할 수 있다. |
Author | MISHAELI MICHAEL SHWARTSMAN STANISLAV YOAZ ADI RAPPOPORT LIHU LEVY OFER SPERBER ZEEV MAKOVSKY LEV |
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Snippet | According to one aspect of the present invention, a processor includes a decode unit decoding a thread pause instruction from a first thread. A back end part... |
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SubjectTerms | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
Title | THREAD PAUSE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS |
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