METHOD AND APPARATUS OF REDUCING LEAKAGE POWER IN MULTIPLE PORT SRAM MEMORY CELL

Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states o...

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Bibliographic Details
Main Authors HOFF DAVID PAUL, GARG MANISH, PHAN MICHAEL THAITHANH
Format Patent
LanguageEnglish
Korean
Published 26.06.2014
Subjects
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