METHOD AND APPARATUS OF REDUCING LEAKAGE POWER IN MULTIPLE PORT SRAM MEMORY CELL
Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states o...
Saved in:
Main Authors | , , |
---|---|
Format | Patent |
Language | English Korean |
Published |
26.06.2014
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Be the first to leave a comment!