METHOD AND APPARATUS OF REDUCING LEAKAGE POWER IN MULTIPLE PORT SRAM MEMORY CELL

Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states o...

Full description

Saved in:
Bibliographic Details
Main Authors HOFF DAVID PAUL, GARG MANISH, PHAN MICHAEL THAITHANH
Format Patent
LanguageEnglish
Korean
Published 26.06.2014
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells, such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells, wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations.
Bibliography:Application Number: KR20147011835