DYNAMIC QUADRATURE CLOCK CORRECTION FOR A PHASE ROTATOR SYSTEM
PURPOSE: A duty cycle, an orthogonal relation, and a dynamic orthogonal clock correction system are provided to reduce a data sample clock jitter by compensating for a mismatch effect in a clock dividing circuit. CONSTITUTION: At least two input signals including at least one in-phase clock and a si...
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Format | Patent |
Language | English Korean |
Published |
03.01.2011
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Abstract | PURPOSE: A duty cycle, an orthogonal relation, and a dynamic orthogonal clock correction system are provided to reduce a data sample clock jitter by compensating for a mismatch effect in a clock dividing circuit. CONSTITUTION: At least two input signals including at least one in-phase clock and a single orthogonal clock is controlled. The adjusted orthogonal clock signal is applied to a device which generates a four-quadrant interpolated output clock phase. The interpolated output clock phase is delayed in order to form a clock for a measurement device. At least two adjusted input signal are measured in the range of the interpolated output clock phase. Errors regarding the in-phase clock and the orthogonal clock are determined by using the sampled information from the measurement device. By using the determined error information, the in-phase clock and the orthogonal clock are adapted to a closed loop feedback configuration. A signal measurement function part(157) includes an offset buffer, an offset DAC, and a determination latch. |
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AbstractList | PURPOSE: A duty cycle, an orthogonal relation, and a dynamic orthogonal clock correction system are provided to reduce a data sample clock jitter by compensating for a mismatch effect in a clock dividing circuit. CONSTITUTION: At least two input signals including at least one in-phase clock and a single orthogonal clock is controlled. The adjusted orthogonal clock signal is applied to a device which generates a four-quadrant interpolated output clock phase. The interpolated output clock phase is delayed in order to form a clock for a measurement device. At least two adjusted input signal are measured in the range of the interpolated output clock phase. Errors regarding the in-phase clock and the orthogonal clock are determined by using the sampled information from the measurement device. By using the determined error information, the in-phase clock and the orthogonal clock are adapted to a closed loop feedback configuration. A signal measurement function part(157) includes an offset buffer, an offset DAC, and a determination latch. |
Author | KELLY WILLIAM RICHARD HSU CHUN MING CLEMENTS STEVEN MARK BEUKEMA TROY JAMES MAY ELIZABETH M RYLOV SERGEY V |
Author_xml | – fullname: HSU CHUN MING – fullname: BEUKEMA TROY JAMES – fullname: CLEMENTS STEVEN MARK – fullname: MAY ELIZABETH M – fullname: KELLY WILLIAM RICHARD – fullname: RYLOV SERGEY V |
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Snippet | PURPOSE: A duty cycle, an orthogonal relation, and a dynamic orthogonal clock correction system are provided to reduce a data sample clock jitter by... |
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SubjectTerms | AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
Title | DYNAMIC QUADRATURE CLOCK CORRECTION FOR A PHASE ROTATOR SYSTEM |
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