A CONTROLLER FOR A MULTIPLE BIT PER CELL NAND FLASH MEMORY FOR EMULATING A SINGLE BIT PER CELL NAND FLASH MEMORY

• Main Authors: BAR OR SHAHAR, MARCU ALON, INBAR DAN, STERN ORI
• Format: Patent
• Language: English; Korean
• Published: 20.10.2010
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; INFORMATION STORAGE; PHYSICS; STATIC STORES

A controller for one type of NAND flash memory device that emulates another type of NAND flash memory device. The controller may include a host NAND interface to receive host data from a NAND host device, and a data aggregator for aggregating the host data with complementary data, to thereby create device data that is storable in a device page of an array of NAND flash memory cells of the NAND flash memory device. After creating the device data the controller writes the device data into a device page of the NAND flash memory cells. The controller also includes a data parser to parse host data from device data when data read operations are executed by the controller. If required, the controller uses the data parser to parse complementary data from device data to create device data when data writing operations are executed by the controller.