WAFER-LEVEL FABRICATION OF LIDDED CHIPS WITH ELECTRODEPOSITED DIELECTRIC COATING
A unit including a semiconductor element, e.g., a chip-scale package (350, 1350) or an optical sensor unit (10) is fabricated. A semiconductor element (300) has semiconductive or conductive material (316) exposed at at least one of the front (302) and rear surfaces (114) and conductive features (310...
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Main Authors | , , , , , , , , , |
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Format | Patent |
Language | English Korean |
Published |
02.09.2009
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Subjects | |
Online Access | Get full text |
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Summary: | A unit including a semiconductor element, e.g., a chip-scale package (350, 1350) or an optical sensor unit (10) is fabricated. A semiconductor element (300) has semiconductive or conductive material (316) exposed at at least one of the front (302) and rear surfaces (114) and conductive features (310) exposed thereat which are insulated from the semiconductive or conductive material. By electrodeposition, an insulative layer (304) is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts (308) and a plurality of conductive traces (306) are formed overlying the electrodeposited insulative layer (304) which connect the conductive features (310) to the conductive contacts (308). An optical sensor unit (10) can be incorporated in a camera module (1030) having an optical element (1058) in registration with an imaging area (1026) of the semiconductor element (1000). |
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Bibliography: | Application Number: KR20097011216 |