EFFICIENT MEMORY HIERARCHY MANAGEMENT
In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and software techniques are provided for fetching an instruction in the data cache after having a miss in an instruction cache to improve the pro...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English |
Published |
13.10.2008
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and software techniques are provided for fetching an instruction in the data cache after having a miss in an instruction cache to improve the processor's performance. If an instruction is not present in the instruction cache, an instruction fetch address is sent as a data fetch address to the data cache. If there is valid data present in the data cache at the supplied instruction fetch address, the data actually is an instruction and the data cache entry is fetched and supplied as an instruction to the processor complex. An additional bit may be included in an instruction page table to indicate on a miss in the instruction cache that the data cache should be checked for the instruction. |
---|---|
AbstractList | In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and software techniques are provided for fetching an instruction in the data cache after having a miss in an instruction cache to improve the processor's performance. If an instruction is not present in the instruction cache, an instruction fetch address is sent as a data fetch address to the data cache. If there is valid data present in the data cache at the supplied instruction fetch address, the data actually is an instruction and the data cache entry is fetched and supplied as an instruction to the processor complex. An additional bit may be included in an instruction page table to indicate on a miss in the instruction cache that the data cache should be checked for the instruction. |
Author | MORROW MICHAEL WILLIAM SARTORIUS THOMAS ANDREW |
Author_xml | – fullname: SARTORIUS THOMAS ANDREW – fullname: MORROW MICHAEL WILLIAM |
BookMark | eNrjYmDJy89L5WRQdXVz83T2dPULUfB19fUPilTw8HQNcgxy9ohU8HX0c3R39QXK8TCwpiXmFKfyQmluBmU31xBnD93Ugvz41OKCxOTUvNSSeO8gIwMDCwMDS0MTC0NHY-JUAQAZAyXq |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences Physics |
ExternalDocumentID | KR20080091481A |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_KR20080091481A3 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 14:00:27 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_KR20080091481A3 |
Notes | Application Number: KR20087020033 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20081013&DB=EPODOC&CC=KR&NR=20080091481A |
ParticipantIDs | epo_espacenet_KR20080091481A |
PublicationCentury | 2000 |
PublicationDate | 20081013 |
PublicationDateYYYYMMDD | 2008-10-13 |
PublicationDate_xml | – month: 10 year: 2008 text: 20081013 day: 13 |
PublicationDecade | 2000 |
PublicationYear | 2008 |
RelatedCompanies | QUALCOMM INCORPORATED |
RelatedCompanies_xml | – name: QUALCOMM INCORPORATED |
Score | 2.7219353 |
Snippet | In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
Title | EFFICIENT MEMORY HIERARCHY MANAGEMENT |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20081013&DB=EPODOC&locale=&CC=KR&NR=20080091481A |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1ZS8NAEB5qPd80WjyqBNS8BXNsQ3wIYnOQWtKUEKV9Kpt0A4KkxUT8-84uie1TX2dgL5idb-f4FuBBz7WMGVauUrswVfS3TLWtnKqDZaYzYvPyJh7viCZW-E7eZoNZB77aXhjBE_oryBHRonK091rc1-tNEMsTtZXVU_aJotVLkDqe0r6OOV2VqXhDx5_GXuwqruuME2WSCB3CCQT_-use7HMgzZn2_Y8h70tZbzuV4BQOpjheWZ9Bh5USHLvt32sSHEVNyluCQ1GjmVcobOywOodHhJcjHh5K5ciP4mQuhyM_4Ymfubzh6L-A-8BP3VDFmRf_G12Mk-1lmj3olquSXYLMG1hR-myTZUE0QqlhUsQBVCMM3YtWXEF_10jXu9U3cGI0LK-62Ydu_f3DbtHV1tmdOKE_dBh8Tg |
link.rule.ids | 230,309,786,891,25594,76906 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LT4NAEJ7U-qg3RY2PqiQqNyKULeKhMRZoQAo0BE17IkC3iYmhjWD8-85uwPbU60yyr2R2vp3HtwD3aq5ktKfncmosNBn9LZUNPU_l_jxTKTFYeROLd_iB7ryTt2l_2oKvpheG84T-cnJEtKgc7b3i9_VqHcSyeG1l-Zh9omj5MooHltS8jhldlSZZw4E9Ca3QlExz4EVSEHEdwgkE_-rrDuw-MX5eBp4-hqwvZbXpVEZHsDfB8YrqGFq0EKBjNn-vCXDg1ylvAfZ5jWZeorC2w_IEHhBeuiw8FIu-7YfRTHRcO2KJn5m45ug_hbuRHZuOjDMn_xtNvGhzmdoZtItlQc9BZA2sKH02yHxBFJKmPS1FHJAqhKJ7URYX0N020uV29S10nNgfJ2M38K7gsFczvqpaF9rV9w-9RrdbZTf8tP4AbKF_Ow |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=EFFICIENT+MEMORY+HIERARCHY+MANAGEMENT&rft.inventor=SARTORIUS+THOMAS+ANDREW&rft.inventor=MORROW+MICHAEL+WILLIAM&rft.date=2008-10-13&rft.externalDBID=A&rft.externalDocID=KR20080091481A |