FUSE REGIONS IN A SEMICONDUCTOR MEMORY DEVICE AND METHODS OF FABRICATING THE SAME

A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation...

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Main Authors BANG, JEONG HO, LEE, KUN GU, PANG, KWANG KYU, SHIN, KYEONG SEON, CHOI, SEUNG GYOO, LYU, KYOUNG SUK, CHOI, HO JEONG
Format Patent
LanguageEnglish
Published 27.10.2005
Edition7
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Abstract A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.
AbstractList A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.
Author LEE, KUN GU
SHIN, KYEONG SEON
BANG, JEONG HO
LYU, KYOUNG SUK
CHOI, HO JEONG
PANG, KWANG KYU
CHOI, SEUNG GYOO
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– fullname: LYU, KYOUNG SUK
– fullname: CHOI, HO JEONG
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Snippet A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
Title FUSE REGIONS IN A SEMICONDUCTOR MEMORY DEVICE AND METHODS OF FABRICATING THE SAME
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