FUSE REGIONS IN A SEMICONDUCTOR MEMORY DEVICE AND METHODS OF FABRICATING THE SAME
A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation...
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Main Authors | , , , , , , |
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Format | Patent |
Language | English |
Published |
27.10.2005
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns. |
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Bibliography: | Application Number: KR20040027486 |