COLUMN DECODER CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE, ESPECIALLY REDUCING CHIP SIZE BY USING FOUR NOR GATES

PURPOSE: A column decoder circuit of a semiconductor memory device is provided to reduce the chip size and to reduce the processing speed delay in a read/write mode through using four NOR gates. CONSTITUTION: A column decoder circuit of a semiconductor memory device comprises plural NMOS transistors...

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Bibliographic Details
Main Authors CHOI, BYUNG GIL, KWAK, CHOONG KEUN
Format Patent
LanguageEnglish
Korean
Published 14.01.2005
Edition7
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PURPOSE: A column decoder circuit of a semiconductor memory device is provided to reduce the chip size and to reduce the processing speed delay in a read/write mode through using four NOR gates. CONSTITUTION: A column decoder circuit of a semiconductor memory device comprises plural NMOS transistors(60-90); plural gate circuits(301-30n) for generating a switching control signal for selecting a bit line of a column group after logic combining between a decoding signal(YA) from the global column decoder for selecting a bit line and a decoding signal(YB) from the global column decoder for selecting a column group; plural bit line selectors(401-40n) for connecting the corresponding bit line to the corresponding data line according to the switching control signal from the gate circuits. Wherein the plural gate circuits consist of four NOR gates(50, 52, 54, 56).
Bibliography:Application Number: KR20030045512