STACKED SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

• Main Author: LEE, CHAN SEOK
• Format: Patent
• Language: English; Korean
• Published: 27.08.2004
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PURPOSE: A stacked semiconductor package and a fabricating method thereof are provided to enhance the performance by improving a method for stacking semiconductor chips and a method for bonding a wire. CONSTITUTION: A lead frame(110) includes a connector. A bottom semiconductor chip(200) includes the first and the second bond pads and is loaded on the lead frame. An intermediate semiconductor chip(300A,300B) includes the first and the second bond pads and is loaded on the bottom semiconductor chip. A top semiconductor chip(400) includes the first and the second bond pads and is loaded on the intermediate semiconductor chips. The first connection part(130) is used for connecting the second bond pad to bottom semiconductor chip, the intermediate semiconductor chip, and the top semiconductor chip. The second connection part(140) is used for connecting the first bond pad to the connector of the lead frame. A sealing resin(150) is used for sealing up the semiconductor chips, the connection parts, and a part of the lead frame.