Semiconductor memory device

PURPOSE: A semiconductor memory device is provided to improve the chip stability by distributing consumption of a peak current. CONSTITUTION: An auto refresh unit(1) outputs an auto refresh signal in an auto refresh mode. An internal counter(2) receives the auto refresh signal to sequentially count...

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Main Author YOON, JI YUN
Format Patent
LanguageEnglish
Korean
Published 10.06.2004
Edition7
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Abstract PURPOSE: A semiconductor memory device is provided to improve the chip stability by distributing consumption of a peak current. CONSTITUTION: An auto refresh unit(1) outputs an auto refresh signal in an auto refresh mode. An internal counter(2) receives the auto refresh signal to sequentially count an internal address by increasing its value and output the counted internal address. Delays(3,4,5) are respectively provided in each of banks(7-9) except a first bank(6). The delays(3,4,5) delay the counted internal address outputted from the internal counter(2) to sequentially transmit it to the respective banks(6-9), thereby forcing the respective banks(6-9) to perform a refresh operation sequentially. The delays(3,4,5) are divided into two groups: one of which is consist of one delay unit and the other is consist of two delays. 본 발명은 뱅크별로 순차적으로 리프레시 동작을 수행하여, 피크전류 소모를 분산시킬 수 있는 반도체 메모리 장치에 관한 것으로서, 오토리프레시 명령을 출력하는 오토리프레시부와, 오토리프레시 명령을 수신하여 내부어드레스를 순차적으로 카운팅하여 출력하는 내부 카운터 및 각 뱅크마다 구비되어, 상기 내부 카운터로부터 출력된 각각의 내부어드레스를 뱅크에 순차적으로 지연시켜 전달하는 딜레이부를 구비하여, 오토리프레시 동작시에 발생하는 피크전류를 감소시키는 것을 특징으로 한다.
AbstractList PURPOSE: A semiconductor memory device is provided to improve the chip stability by distributing consumption of a peak current. CONSTITUTION: An auto refresh unit(1) outputs an auto refresh signal in an auto refresh mode. An internal counter(2) receives the auto refresh signal to sequentially count an internal address by increasing its value and output the counted internal address. Delays(3,4,5) are respectively provided in each of banks(7-9) except a first bank(6). The delays(3,4,5) delay the counted internal address outputted from the internal counter(2) to sequentially transmit it to the respective banks(6-9), thereby forcing the respective banks(6-9) to perform a refresh operation sequentially. The delays(3,4,5) are divided into two groups: one of which is consist of one delay unit and the other is consist of two delays. 본 발명은 뱅크별로 순차적으로 리프레시 동작을 수행하여, 피크전류 소모를 분산시킬 수 있는 반도체 메모리 장치에 관한 것으로서, 오토리프레시 명령을 출력하는 오토리프레시부와, 오토리프레시 명령을 수신하여 내부어드레스를 순차적으로 카운팅하여 출력하는 내부 카운터 및 각 뱅크마다 구비되어, 상기 내부 카운터로부터 출력된 각각의 내부어드레스를 뱅크에 순차적으로 지연시켜 전달하는 딜레이부를 구비하여, 오토리프레시 동작시에 발생하는 피크전류를 감소시키는 것을 특징으로 한다.
Author YOON, JI YUN
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Title Semiconductor memory device
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