METHOD FOR TESTING MEMORY MODULE
PURPOSE: A method for testing a memory module is provided to improve the reliability as to the test result, by enabling a probe pin to contact a solder ball directly even under the state that a plurality of semiconductor packages are mounted on a substrate by mediating the solder ball. CONSTITUTION:...
Saved in:
Main Author | |
---|---|
Format | Patent |
Language | English Korean |
Published |
09.07.2001
|
Edition | 7 |
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | PURPOSE: A method for testing a memory module is provided to improve the reliability as to the test result, by enabling a probe pin to contact a solder ball directly even under the state that a plurality of semiconductor packages are mounted on a substrate by mediating the solder ball. CONSTITUTION: A chip size package(P) has a plurality of solder balls(S) arranged in a grid on its bottom. The solder balls are connected electrically by a test pattern(T) each other. Therefore, the test pattern has both ends, and both ends of the test pattern are revealed at the chip size package. And a probing pad(D) is formed to contact a probe pin on each end. Eight chip size packages having the test pattern and the probing pad are mounted on a substrate(B). Two adjacent probing pads are connected by the test pattern. Therefore, the solder balls of all chip size packages are connected electrically by the test pattern, one outer probing pad of two probing pads of two chip size packages arranged on the outermost part is not connected to another one. |
---|---|
AbstractList | PURPOSE: A method for testing a memory module is provided to improve the reliability as to the test result, by enabling a probe pin to contact a solder ball directly even under the state that a plurality of semiconductor packages are mounted on a substrate by mediating the solder ball. CONSTITUTION: A chip size package(P) has a plurality of solder balls(S) arranged in a grid on its bottom. The solder balls are connected electrically by a test pattern(T) each other. Therefore, the test pattern has both ends, and both ends of the test pattern are revealed at the chip size package. And a probing pad(D) is formed to contact a probe pin on each end. Eight chip size packages having the test pattern and the probing pad are mounted on a substrate(B). Two adjacent probing pads are connected by the test pattern. Therefore, the solder balls of all chip size packages are connected electrically by the test pattern, one outer probing pad of two probing pads of two chip size packages arranged on the outermost part is not connected to another one. |
Author | LEE, JEONG GU |
Author_xml | – fullname: LEE, JEONG GU |
BookMark | eNrjYmDJy89L5WRQ8HUN8fB3UXDzD1IIcQ0O8fRzBwr5-gdFKvj6u4T6uPIwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUknjvICMDA0MDAzMTY0tjR2PiVAEAXlMkfg |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
Edition | 7 |
ExternalDocumentID | KR20010064393A |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_KR20010064393A3 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 16:27:38 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English Korean |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_KR20010064393A3 |
Notes | Application Number: KR19990064583 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010709&DB=EPODOC&CC=KR&NR=20010064393A |
ParticipantIDs | epo_espacenet_KR20010064393A |
PublicationCentury | 2000 |
PublicationDate | 20010709 |
PublicationDateYYYYMMDD | 2001-07-09 |
PublicationDate_xml | – month: 07 year: 2001 text: 20010709 day: 09 |
PublicationDecade | 2000 |
PublicationYear | 2001 |
RelatedCompanies | HYNIX SEMICONDUCTOR INC |
RelatedCompanies_xml | – name: HYNIX SEMICONDUCTOR INC |
Score | 2.5033455 |
Snippet | PURPOSE: A method for testing a memory module is provided to improve the reliability as to the test result, by enabling a probe pin to contact a solder ball... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | METHOD FOR TESTING MEMORY MODULE |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010709&DB=EPODOC&locale=&CC=KR&NR=20010064393A |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfR3LSsNAcKhV1JtWpWqVgJLb4tY8NnsIYpON0ZqkxFTqqTQxAVFssRF_38m20Z56W2Zg9gHzfizAJaeFZhrcIoXZLYjOqUHQCuckZ9qEVYE3KkdsBKHpD_WHkTFqwEfdCyPnhP7I4YjIURnyeynl9ew_iOXK2sr5VfqGoOmNl9iuWnvHSJpy1e3ZYhC5kaM6jt2P1TBe4KT61W43YBMNaVbxg3juVX0ps1Wl4u3B1gDpfZb70HiftmDHqf9ea8F2sEx543LJffMDUAKR-JGroOOmJOIpuQ_vEBRE8YsSRO7wURzChScSxye41fjvZuN-vHou7Qia6PPnbVBQTWupZXWzgl3r2avFJ5RV-XKuozzgqXUMnXWUTtajT2F3UUrFCOUdaJZf3_kZ6tYyPZdP8guAcHZx |
link.rule.ids | 230,309,783,888,25576,76876 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfR3JSsNA9FGrWG9aFZeqASW3YGqWyRyK2CymZitxKu0pNDEBUWyxEX_fl2mjPfU2vAdvFnj7MgA3VC4UXaOGVOjdQlKprElohVMpJ8qUVIE3mY_YCELdHalPY23cgI-6F4bPCf3hwxGRozLk95LL6_l_EMvitZWL2_QNQbN7h_UssfaOkbRMRavfs4eRFZmiafa8WAzjJY6rX-VhC7bRyCYVP9gv_aovZb6uVJx92Bkivc_yABrvsza0zPrvtTbsBquUNy5X3Lc4BCGwmRtZAjpuArOf2SB8RFAQxRMhiKyRbx_BtWMz05Vwq-TvZokXr59LOYYm-vz5CQioppXUMLpZQe7U7NWgU5lU-XKqojygqXEKnU2Uzjajr6DlssBP_EHoncPesqyKSDLtQLP8-s4vUM-W6SV_nl85K3lk |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=METHOD+FOR+TESTING+MEMORY+MODULE&rft.inventor=LEE%2C+JEONG+GU&rft.date=2001-07-09&rft.externalDBID=A&rft.externalDocID=KR20010064393A |