NONVOLATILE MEMORY DEVICE AND METHOD THEREOF

PURPOSE: A nonvolatile memory device and manufacturing method thereof are provided to decrease a number of common source line necessary to total cell array region by using a source pad line. CONSTITUTION: The memory device comprises a plurality of active regions(105) defined by a plurality of isolat...

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Bibliographic Details
Main Authors CHOE, JUNG HYUK, KIM, JONG HAN
Format Patent
LanguageEnglish
Korean
Published 07.02.2000
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PURPOSE: A nonvolatile memory device and manufacturing method thereof are provided to decrease a number of common source line necessary to total cell array region by using a source pad line. CONSTITUTION: The memory device comprises a plurality of active regions(105) defined by a plurality of isolation regions(102) and formed on a semiconductor substrate(100); a plurality of stacked gates having a plurality of floating gates(110) and control gates(120); a plurality of source region(135) formed in the active region and between the stacked gates(110, 120); a plurality of contact holes(145) self-aligned by the stacked gates and formed in an interlayer dielectric(136P); a plurality of source pad lines(145') formed in the contact holes(145) for connecting the exposed source regions parallel to the stacked gates; and a common source line(180) arranged parallel to the stacked gates. By connecting the source regions(135) to the source pad lines(145') made of a low resistivity metal, the cell array area is reduced. 비휘발성 메모리 장치 및 그 제조 방법에 관해 개시한다. 본 발명에 따른 비휘발성 메모리 장치는 이웃한 셀들간의 소오스 영역들을 워드 라인과 평행한 방향으로 연결하는 소오스 패드 라인을 구비한다. 따라서, 전체 셀 에레이 영역에 필요한 공통 소오스 라인의 수를 감소시킬 수 있다. 또, 자기 정렬된 비트 라인 콘택홀을 구비하여 워드 라인과 비트라인 콘택홀간의 거리를 최소화하여 셀 어레이 영역의 크기를 최소화할 수 있다.
Bibliography:Application Number: KR19980028036