TESTING METHOD FOR A SEMICONDUCTOR MEMORY DEVICE

• Main Authors: YANAGISAWA, KAZUMASA, KATSUKAWA, KORO, OUJI, YOSHIAKI, NAKAMURA, MASAYUKI, NOZOE, ATSUSHI, MATSUMOTO, TETSURO, KOBAYASHI, YUTAKA, ISHII, KYOKO, MISASHI, WAZUO, KINOSHITA, YOSHITAKA, WADA, SHOJI, OTA, TATSUYUKI, UDAKAWA, TETSU, MIWA, HITOSHI, TSUKADA, HIROMI
• Format: Patent
• Language: English
• Published: 17.08.1998
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; CONTROLLING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; REGULATING; SEMICONDUCTOR DEVICES; STATIC STORES; SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES

A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line sele...