EEPROM DEVICE
PURPOSE:To prevent the reduction in the level margin by switching a reference voltage fed to a differential type sense amplifier to a level according to a read signal level changed in response to number of times of writing to a memory cell. CONSTITUTION:A sense amplifier SA discriminates a high/low...
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Format | Patent |
Language | English |
Published |
08.02.1988
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Abstract | PURPOSE:To prevent the reduction in the level margin by switching a reference voltage fed to a differential type sense amplifier to a level according to a read signal level changed in response to number of times of writing to a memory cell. CONSTITUTION:A sense amplifier SA discriminates a high/low level for a read signal outputted to a common data line CD by the addressing of a memory array M-ARY while referencing the reference voltage of a voltage generating circuit. In case of lots of rewriting number of times to a MNOS transistor, a voltage generating circuit forming two reference voltages where a threshold voltage is shifted toward the high level is provided. One is used for a reference voltage forming when number of times of rewriting is comparatively less and the other is used to form a reference voltage when number of times of rewriting exceeds a prescribed number of times, and a switching signal S is supplied to a gate of a switch MOSFETQ17 corresponding to a column switch from the counter circuit. Thus, the reference voltage attended with the rewriting number of times is switched and the operating margin is improved and the desired data storage characteristic is obtained. |
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AbstractList | PURPOSE:To prevent the reduction in the level margin by switching a reference voltage fed to a differential type sense amplifier to a level according to a read signal level changed in response to number of times of writing to a memory cell. CONSTITUTION:A sense amplifier SA discriminates a high/low level for a read signal outputted to a common data line CD by the addressing of a memory array M-ARY while referencing the reference voltage of a voltage generating circuit. In case of lots of rewriting number of times to a MNOS transistor, a voltage generating circuit forming two reference voltages where a threshold voltage is shifted toward the high level is provided. One is used for a reference voltage forming when number of times of rewriting is comparatively less and the other is used to form a reference voltage when number of times of rewriting exceeds a prescribed number of times, and a switching signal S is supplied to a gate of a switch MOSFETQ17 corresponding to a column switch from the counter circuit. Thus, the reference voltage attended with the rewriting number of times is switched and the operating margin is improved and the desired data storage characteristic is obtained. |
Author | SATO NOBUYUKI NAGAI YOSHIKAZU NABEYA SHINJI |
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Notes | Application Number: JP19860171651 |
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PublicationYear | 1988 |
RelatedCompanies | HITACHI LTD HITACHI VLSI ENG CORP |
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Snippet | PURPOSE:To prevent the reduction in the level margin by switching a reference voltage fed to a differential type sense amplifier to a level according to a read... |
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SubjectTerms | INFORMATION STORAGE PHYSICS STATIC STORES |
Title | EEPROM DEVICE |
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